Commit 1b79fc4f authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Rafael J. Wysocki
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x86/apb_timer: Remove driver for deprecated platform 



Intel Moorestown and Medfield are quite old Intel Atom based
32-bit platforms, which were in limited use in some Android phones,
tablets and consumer electronics more than eight years ago.

There are no bugs or problems ever reported outside from Intel
for breaking any of that platforms for years. It seems no real
users exists who run more or less fresh kernel on it. Commit
05f4434b ("ASoC: Intel: remove mfld_machine") is also in align
with this theory.

Due to above and to reduce a burden of supporting outdated drivers,
remove the support for outdated platforms completely.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 2468f933

Documentation/admin-guide/kernel-parameters.txt

+0 −6
Original line number Diff line number Diff line
@@ -5932,12 +5932,6 @@ 
			default x2apic cluster mode on platforms

			supporting x2apic.



	x86_intel_mid_timer= [X86-32,APBT]

			Choose timer option for x86 Intel MID platform.

			Two valid options are apbt timer only and lapic timer

			plus one apbt timer for broadcast timer.

			x86_intel_mid_timer=apbt_only | lapic_and_apbt



	xen_512gb_limit		[KNL,X86-64,XEN]

			Restricts the kernel running paravirtualized under Xen

			to use only up to 512 GB of RAM. The reason to do so is

arch/x86/Kconfig

+0 −12
Original line number Diff line number Diff line
@@ -892,18 +892,6 @@ config HPET_EMULATE_RTC 
	def_bool y

	depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)



config APB_TIMER

	def_bool y if X86_INTEL_MID

	prompt "Intel MID APB Timer Support" if X86_INTEL_MID

	select DW_APB_TIMER

	depends on X86_INTEL_MID && SFI

	help

	 APB timer is the replacement for 8254, HPET on X86 MID platforms.

	 The APBT provides a stable time base on SMP

	 systems, unlike the TSC, but it is more expensive to access,

	 as it is off-chip. APB timers are always running regardless of CPU

	 C states, they are used as per CPU clockevent device when possible.



# Mark as expert because too many people got it wrong.

# The code disables itself when not needed.

config DMI

arch/x86/include/asm/apb_timer.h

deleted100644 → 0
+0 −40
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare

 *

 * (C) Copyright 2009 Intel Corporation

 * Author: Jacob Pan (jacob.jun.pan@intel.com)

 *

 * Note:

 */



#ifndef ASM_X86_APBT_H

#define ASM_X86_APBT_H

#include <linux/sfi.h>



#ifdef CONFIG_APB_TIMER



/* default memory mapped register base */

#define LNW_SCU_ADDR           0xFF100000

#define LNW_EXT_TIMER_OFFSET   0x1B800

#define APBT_DEFAULT_BASE      (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)

#define LNW_EXT_TIMER_PGOFFSET         0x800



/* APBT clock speed range from PCLK to fabric base, 25-100MHz */

#define APBT_MAX_FREQ          50000000

#define APBT_MIN_FREQ          1000000

#define APBT_MMAP_SIZE         1024



extern void apbt_time_init(void);

extern void apbt_setup_secondary_clock(void);



extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);

extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);

extern int sfi_mtimer_num;



#else /* CONFIG_APB_TIMER */



static inline void apbt_time_init(void) { }



#endif

#endif /* ASM_X86_APBT_H */

arch/x86/include/asm/intel-mid.h

+0 −11
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ extern void intel_mid_pwr_power_off(void); 
extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);



extern int get_gpio_by_name(const char *name);

extern int __init sfi_parse_mtmr(struct sfi_table_header *table);



/*

 * Here defines the array of devices platform data that IAFW would export
@@ -91,14 +90,6 @@ static inline void intel_scu_devices_destroy(void) { } 


#endif /* !CONFIG_X86_INTEL_MID */



enum intel_mid_timer_options {

	INTEL_MID_TIMER_DEFAULT,

	INTEL_MID_TIMER_APBT_ONLY,

	INTEL_MID_TIMER_LAPIC_APBT,

};



extern enum intel_mid_timer_options intel_mid_timer_options;



/* Bus Select SoC Fuse value */

#define BSEL_SOC_FUSE_MASK		0x7

/* FSB 133MHz */
@@ -108,8 +99,6 @@ extern enum intel_mid_timer_options intel_mid_timer_options; 
/* FSB 83MHz */

#define BSEL_SOC_FUSE_111		0x7



#define SFI_MTMR_MAX_NUM		8



/* The offset for the mapping of global gpio pin to irq */

#define INTEL_MID_IRQ_OFFSET		0x100

arch/x86/kernel/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -116,7 +116,6 @@ obj-$(CONFIG_VM86) += vm86_32.o 
obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o



obj-$(CONFIG_HPET_TIMER) 	+= hpet.o

obj-$(CONFIG_APB_TIMER)		+= apb_timer.o



obj-$(CONFIG_AMD_NB)		+= amd_nb.o

obj-$(CONFIG_DEBUG_NMI_SELFTEST) += nmi_selftest.o