dt-bindings: pinctrl: qcom,sc7180: convert to dtschema

Qualcomm Technologies, Inc. SC7180 TLMM block

This binding describes the Top Level Mode Multiplexer block found in the

SC7180 platform.

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sc7180-pinctrl"

- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: the base address and size of the north, south and west

		    TLMM tiles

- reg-names:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: names for the cells of reg, must contain "north", "south"

		    and "west".

- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: should specify the TLMM summary IRQ.

- interrupt-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as an interrupt controller

- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/interrupt-controller/irq.h>

- gpio-controller:

	Usage: required

	Value type: <none>

	Definition: identifies this node as a gpio controller

- #gpio-cells:

	Usage: required

	Value type: <u32>

	Definition: must be 2. Specifying the pin number and flags, as defined

		    in <dt-bindings/gpio/gpio.h>

- gpio-ranges:

	Usage: required

	Value type: <prop-encoded-array>

	Definition:  see ../gpio/gpio.txt

- gpio-reserved-ranges:

	Usage: optional

	Value type: <prop-encoded-array>

	Definition: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

- pins:

	Usage: required

	Value type: <string-array>

	Definition: List of gpio pins affected by the properties specified in

		    this subnode.

		    Valid pins are:

		      gpio0-gpio118

		        Supports mux, bias and drive-strength

		      sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,

		      sdc2_data sdc1_rclk

		        Supports bias and drive-strength

		      ufs_reset

			Supports bias and drive-strength

- function:

	Usage: required

	Value type: <string>

	Definition: Specify the alternative function to be configured for the

		    specified pins. Functions are only valid for gpio pins.

		    Valid values are:

		    adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,

		    atest_char1, atest_char2, atest_char3, atest_tsens,

		    atest_tsens2, atest_usb1, atest_usb10, atest_usb11,

		    atest_usb12, atest_usb13, atest_usb2, atest_usb20,

		    atest_usb21, atest_usb22, atest_usb23, audio_ref,

		    btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,

		    cci_timer1, cci_timer2, cci_timer3, cci_timer4,

		    cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,

		    ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,

		    gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,

		    jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,

		    mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,

		    mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,

		    PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,

		    qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,

		    qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,

		    qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,

		    qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,

		    sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,

		    tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,

		    usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,

		    vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,

		    wlan2_adc1,

- bias-disable:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as no pull.

- bias-pull-down:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull down.

- bias-pull-up:

	Usage: optional

	Value type: <none>

	Definition: The specified pins should be configured as pull up.

- output-high:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    high.

		    Not valid for sdc pins.

- output-low:

	Usage: optional

	Value type: <none>

	Definition: The specified pins are configured in output mode, driven

		    low.

		    Not valid for sdc pins.

- drive-strength:

	Usage: optional

	Value type: <u32>

	Definition: Selects the drive strength for the specified pins, in mA.

		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16

Example:

	tlmm: pinctrl@3500000 {

		compatible = "qcom,sc7180-pinctrl";

		reg = <0x3500000 0x300000>,

		      <0x3900000 0x300000>,

		      <0x3D00000 0x300000>;

		reg-names = "west", "north", "south";

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-ranges = <&tlmm 0 0 119>;

		gpio-reserved-ranges = <0 4>, <106 4>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7180 TLMM pin controller

maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:

  Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.

properties:

  compatible:

    const: qcom,sc7180-pinctrl

  reg:

    maxItems: 3

  reg-names:

    items:

      - const: west

      - const: north

      - const: south

  interrupts: true

  interrupt-controller: true

  "#interrupt-cells": true

  gpio-controller: true

  "#gpio-cells": true

  gpio-ranges: true

  wakeup-parent: true

  gpio-reserved-ranges:

    minItems: 1

    maxItems: 60

  gpio-line-names:

    maxItems: 119

patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-sc7180-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-sc7180-tlmm-state"

        additionalProperties: false

$defs:

  qcom-sc7180-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"

            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,

                      sdc2_cmd, sdc2_data, ufs_reset ]

        minItems: 1

        maxItems: 36

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,

                atest_char1, atest_char2, atest_char3, atest_tsens,

                atest_tsens2, atest_usb1, atest_usb10, atest_usb11,

                atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,

                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,

                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,

                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,

                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,

                gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,

                jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,

                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,

                mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,

                pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,

                qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,

                qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,

                qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,

                qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,

                sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,

                tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,

                _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,

                wlan1_adc1, wlan2_adc0, wlan2_adc1 ]

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      drive-strength: true

      input-enable: true

      output-high: true

      output-low: true

    required:

      - pins

    additionalProperties: false

allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:

  - compatible

  - reg

  - reg-names

additionalProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@3500000 {

        compatible = "qcom,sc7180-pinctrl";

        reg = <0x03500000 0x300000>,

              <0x03900000 0x300000>,

              <0x03d00000 0x300000>;

        reg-names = "west", "north", "south";

        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

        gpio-ranges = <&tlmm 0 0 120>;

        wakeup-parent = <&pdc>;

        dp_hot_plug_det: dp-hot-plug-det-state {

            pins = "gpio117";

            function = "dp_hot";

        };

        qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {

            spi-pins {

                pins = "gpio53", "gpio54", "gpio55";

                function = "qup15";

            };

            cs-pins {

                pins = "gpio56";

                function = "gpio";

            };

        };

    };