Commit 1b5c0967 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/40x: Remove support for IBM 403GCX 



CONFIG_403GCX is not user selectable and is not
selected by any platform.

Remove it.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/635f8f5ce9d1f761b3bd8dc3e8ddad500cea26c4.1590079968.git.christophe.leroy@csgroup.eu
parent 4e1df545

arch/powerpc/include/asm/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 




/* bytes per L1 cache line */

#if defined(CONFIG_PPC_8xx) || defined(CONFIG_403GCX)

#if defined(CONFIG_PPC_8xx)

#define L1_CACHE_SHIFT		4

#define MAX_COPY_PREFETCH	1

#define IFETCH_ALIGN_SHIFT	2

arch/powerpc/include/asm/reg_booke.h

+0 −54
Original line number Diff line number Diff line
@@ -663,60 +663,6 @@ 
#define EPC_EPID	0x00003fff

#define EPC_EPID_SHIFT	0



/*

 * The IBM-403 is an even more odd special case, as it is much

 * older than the IBM-405 series.  We put these down here incase someone

 * wishes to support these machines again.

 */

#ifdef CONFIG_403GCX

/* Special Purpose Registers (SPRNs)*/

#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */

#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */

#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */

#define SPRN_TBHI	0x3DC	/* Time Base High */

#define SPRN_TBLO	0x3DD	/* Time Base Low */

#define SPRN_DBCR	0x3F2	/* Debug Control Register */

#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */

#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */

#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */

#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */





/* Bit definitions for the DBCR. */

#define DBCR_EDM	DBCR0_EDM

#define DBCR_IDM	DBCR0_IDM

#define DBCR_RST(x)	(((x) & 0x3) << 28)

#define DBCR_RST_NONE	0

#define DBCR_RST_CORE	1

#define DBCR_RST_CHIP	2

#define DBCR_RST_SYSTEM	3

#define DBCR_IC		DBCR0_IC	/* Instruction Completion Debug Evnt */

#define DBCR_BT		DBCR0_BT	/* Branch Taken Debug Event */

#define DBCR_EDE	DBCR0_EDE	/* Exception Debug Event */

#define DBCR_TDE	DBCR0_TDE	/* TRAP Debug Event */

#define DBCR_FER	0x00F80000	/* First Events Remaining Mask */

#define DBCR_FT		0x00040000	/* Freeze Timers on Debug Event */

#define DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */

#define DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */

#define DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */

#define DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */

#define DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */

#define DAC_BYTE	0

#define DAC_HALF	1

#define DAC_WORD	2

#define DAC_QUAD	3

#define DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */

#define DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */

#define DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */

#define DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */

#define DBCR_SED	0x00000020	/* Second Exception Debug Event */

#define DBCR_STD	0x00000010	/* Second Trap Debug Event */

#define DBCR_SIA	0x00000008	/* Second IAC Enable */

#define DBCR_SDA	0x00000004	/* Second DAC Enable */

#define DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */

#define DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */

#endif /* 403GCX */



/* Some 476 specific registers */

#define SPRN_SSPCR		830

#define SPRN_USPCR		831

arch/powerpc/include/asm/time.h

+0 −12
Original line number Diff line number Diff line
@@ -51,24 +51,12 @@ struct div_result { 


static inline unsigned long get_tbl(void)

{

#if defined(CONFIG_403GCX)

	unsigned long tbl;

	asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));

	return tbl;

#else

	return mftbl();

#endif

}



static inline unsigned int get_tbu(void)

{

#ifdef CONFIG_403GCX

	unsigned int tbu;

	asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));

	return tbu;

#else

	return mftbu();

#endif

}

#endif /* !CONFIG_PPC64 */

arch/powerpc/kernel/cputable.c

+0 −37
Original line number Diff line number Diff line
@@ -1232,43 +1232,6 @@ static struct cpu_spec __initdata cpu_specs[] = { 
	},

#endif /* CONFIG_PPC_8xx */

#ifdef CONFIG_40x

	{	/* 403GC */

		.pvr_mask		= 0xffffff00,

		.pvr_value		= 0x00200200,

		.cpu_name		= "403GC",

		.cpu_features		= CPU_FTRS_40X,

		.cpu_user_features	= PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,

		.mmu_features		= MMU_FTR_TYPE_40x,

		.icache_bsize		= 16,

		.dcache_bsize		= 16,

		.machine_check		= machine_check_4xx,

		.platform		= "ppc403",

	},

	{	/* 403GCX */

		.pvr_mask		= 0xffffff00,

		.pvr_value		= 0x00201400,

		.cpu_name		= "403GCX",

		.cpu_features		= CPU_FTRS_40X,

		.cpu_user_features	= PPC_FEATURE_32 |

		 	PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,

		.mmu_features		= MMU_FTR_TYPE_40x,

		.icache_bsize		= 16,

		.dcache_bsize		= 16,

		.machine_check		= machine_check_4xx,

		.platform		= "ppc403",

	},

	{	/* 403G ?? */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x00200000,

		.cpu_name		= "403G ??",

		.cpu_features		= CPU_FTRS_40X,

		.cpu_user_features	= PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,

		.mmu_features		= MMU_FTR_TYPE_40x,

		.icache_bsize		= 16,

		.dcache_bsize		= 16,

		.machine_check		= machine_check_4xx,

		.platform		= "ppc403",

	},

	{	/* 405GP */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x40110000,

arch/powerpc/kernel/head_40x.S

+0 −45
Original line number Diff line number Diff line
@@ -253,21 +253,12 @@ _ENTRY(saved_ksp_limit) 
	START_EXCEPTION(0x1100,	DTLBMiss)

	mtspr	SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */

	mtspr	SPRN_SPRG_SCRATCH1, r11

#ifdef CONFIG_403GCX

	stw     r12, 0(r0)

	stw     r9, 4(r0)

	mfcr    r11

	mfspr   r12, SPRN_PID

	stw     r11, 8(r0)

	stw     r12, 12(r0)

#else

	mtspr	SPRN_SPRG_SCRATCH3, r12

	mtspr	SPRN_SPRG_SCRATCH4, r9

	mfcr	r11

	mfspr	r12, SPRN_PID

	mtspr	SPRN_SPRG_SCRATCH6, r11

	mtspr	SPRN_SPRG_SCRATCH5, r12

#endif

	mfspr	r10, SPRN_DEAR		/* Get faulting address */



	/* If we are faulting a kernel address, we have to use the
@@ -333,21 +324,12 @@ _ENTRY(saved_ksp_limit) 
	/* The bailout.  Restore registers to pre-exception conditions

	 * and call the heavyweights to help us out.

	 */

#ifdef CONFIG_403GCX

	lwz     r12, 12(r0)

	lwz     r11, 8(r0)

	mtspr   SPRN_PID, r12

	mtcr    r11

	lwz     r9, 4(r0)

	lwz     r12, 0(r0)

#else

	mfspr	r12, SPRN_SPRG_SCRATCH5

	mfspr	r11, SPRN_SPRG_SCRATCH6

	mtspr	SPRN_PID, r12

	mtcr	r11

	mfspr	r9, SPRN_SPRG_SCRATCH4

	mfspr	r12, SPRN_SPRG_SCRATCH3

#endif

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r10, SPRN_SPRG_SCRATCH0

	b	DataStorage
@@ -359,21 +341,12 @@ _ENTRY(saved_ksp_limit) 
	START_EXCEPTION(0x1200,	ITLBMiss)

	mtspr	SPRN_SPRG_SCRATCH0, r10	 /* Save some working registers */

	mtspr	SPRN_SPRG_SCRATCH1, r11

#ifdef CONFIG_403GCX

	stw     r12, 0(r0)

	stw     r9, 4(r0)

	mfcr    r11

	mfspr   r12, SPRN_PID

	stw     r11, 8(r0)

	stw     r12, 12(r0)

#else

	mtspr	SPRN_SPRG_SCRATCH3, r12

	mtspr	SPRN_SPRG_SCRATCH4, r9

	mfcr	r11

	mfspr	r12, SPRN_PID

	mtspr	SPRN_SPRG_SCRATCH6, r11

	mtspr	SPRN_SPRG_SCRATCH5, r12

#endif

	mfspr	r10, SPRN_SRR0		/* Get faulting address */



	/* If we are faulting a kernel address, we have to use the
@@ -439,21 +412,12 @@ _ENTRY(saved_ksp_limit) 
	/* The bailout.  Restore registers to pre-exception conditions

	 * and call the heavyweights to help us out.

	 */

#ifdef CONFIG_403GCX

	lwz     r12, 12(r0)

	lwz     r11, 8(r0)

	mtspr   SPRN_PID, r12

	mtcr    r11

	lwz     r9, 4(r0)

	lwz     r12, 0(r0)

#else

	mfspr	r12, SPRN_SPRG_SCRATCH5

	mfspr	r11, SPRN_SPRG_SCRATCH6

	mtspr	SPRN_PID, r12

	mtcr	r11

	mfspr	r9, SPRN_SPRG_SCRATCH4

	mfspr	r12, SPRN_SPRG_SCRATCH3

#endif

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r10, SPRN_SPRG_SCRATCH0

	b	InstructionAccess
@@ -603,21 +567,12 @@ finish_tlb_load: 


	/* Done...restore registers and get out of here.

	*/

#ifdef CONFIG_403GCX

	lwz     r12, 12(r0)

	lwz     r11, 8(r0)

	mtspr   SPRN_PID, r12

	mtcr    r11

	lwz     r9, 4(r0)

	lwz     r12, 0(r0)

#else

	mfspr	r12, SPRN_SPRG_SCRATCH5

	mfspr	r11, SPRN_SPRG_SCRATCH6

	mtspr	SPRN_PID, r12

	mtcr	r11

	mfspr	r9, SPRN_SPRG_SCRATCH4

	mfspr	r12, SPRN_SPRG_SCRATCH3

#endif

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r10, SPRN_SPRG_SCRATCH0

	PPC405_ERR77_SYNC