Commit 1b0c9d00 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-5.17-1' of https://github.com/kvm-riscv/linux into HEAD

KVM/riscv changes for 5.17, take #1

- Use common KVM implementation of MMU memory caches
- SBI v0.2 support for Guest
- Initial KVM selftests support
- Fix to avoid spurious virtual interrupts after clearing hideleg CSR
- Update email address for Anup and Atish
parents 7fd55a02 497685f2
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+2 −0
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@@ -46,10 +46,12 @@ Andy Adamson <andros@citi.umich.edu>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
Archit Taneja <archit@ti.com>
Ard Biesheuvel <ardb@kernel.org> <ard.biesheuvel@linaro.org>
Arnaud Patard <arnaud.patard@rtp-net.org>
Arnd Bergmann <arnd@arndb.de>
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
Axel Dyks <xl@xlsigned.net>
Axel Lin <axel.lin@gmail.com>
Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>
+2 −2
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@@ -10444,8 +10444,8 @@ F: arch/powerpc/kernel/kvm*
F:	arch/powerpc/kvm/
KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)
M:	Anup Patel <anup.patel@wdc.com>
R:	Atish Patra <atish.patra@wdc.com>
M:	Anup Patel <anup@brainfault.org>
R:	Atish Patra <atishp@atishpatra.org>
L:	kvm@vger.kernel.org
L:	kvm-riscv@lists.infradead.org
L:	linux-riscv@lists.infradead.org
+2 −9
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@@ -77,13 +77,6 @@ struct kvm_sbi_context {
	int return_handled;
};

#define KVM_MMU_PAGE_CACHE_NR_OBJS	32

struct kvm_mmu_page_cache {
	int nobjs;
	void *objects[KVM_MMU_PAGE_CACHE_NR_OBJS];
};

struct kvm_cpu_trap {
	unsigned long sepc;
	unsigned long scause;
@@ -193,7 +186,7 @@ struct kvm_vcpu_arch {
	struct kvm_sbi_context sbi_context;

	/* Cache pages needed to program page tables with spinlock held */
	struct kvm_mmu_page_cache mmu_page_cache;
	struct kvm_mmu_memory_cache mmu_page_cache;

	/* VCPU power-off state */
	bool power_off;
@@ -220,12 +213,12 @@ void __kvm_riscv_hfence_gvma_all(void);
int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu,
			 struct kvm_memory_slot *memslot,
			 gpa_t gpa, unsigned long hva, bool is_write);
void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu);
int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm);
void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
void kvm_riscv_stage2_mode_detect(void);
unsigned long kvm_riscv_stage2_mode(void);
int kvm_riscv_stage2_gpa_bits(void);

void kvm_riscv_stage2_vmid_detect(void);
unsigned long kvm_riscv_stage2_vmid_bits(void);
+1 −1
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@@ -2,6 +2,6 @@
#ifndef _ASM_RISCV_KVM_TYPES_H
#define _ASM_RISCV_KVM_TYPES_H

#define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE 40
#define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE 32

#endif /* _ASM_RISCV_KVM_TYPES_H */
+33 −0
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/* SPDX-License-Identifier: GPL-2.0-only */
/**
 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
 *
 * Authors:
 *     Atish Patra <atish.patra@wdc.com>
 */

#ifndef __RISCV_KVM_VCPU_SBI_H__
#define __RISCV_KVM_VCPU_SBI_H__

#define KVM_SBI_IMPID 3

#define KVM_SBI_VERSION_MAJOR 0
#define KVM_SBI_VERSION_MINOR 2

struct kvm_vcpu_sbi_extension {
	unsigned long extid_start;
	unsigned long extid_end;
	/**
	 * SBI extension handler. It can be defined for a given extension or group of
	 * extension. But it should always return linux error codes rather than SBI
	 * specific error codes.
	 */
	int (*handler)(struct kvm_vcpu *vcpu, struct kvm_run *run,
		       unsigned long *out_val, struct kvm_cpu_trap *utrap,
		       bool *exit);
};

void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(unsigned long extid);

#endif /* __RISCV_KVM_VCPU_SBI_H__ */
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