Commit 1b073383 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-core-3.17-3' of git://git.infradead.org/users/jcooper/linux into irq/core 

irqchip core changes for v3.17 (round #3) from Jason Cooper
 * gic: Add GICv3 driver
 * atmel: Move atmel aic driver from arch code to irqchip/
parents d709f7bc f0cf9d2f

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ config ARM64 
	select ARM_AMBA

	select ARM_ARCH_TIMER

	select ARM_GIC

	select ARM_GIC_V3

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

arch/arm64/kernel/head.S

+18 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include <linux/linkage.h>

#include <linux/init.h>

#include <linux/irqchip/arm-gic-v3.h>



#include <asm/assembler.h>

#include <asm/ptrace.h>
@@ -296,6 +297,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 
	msr	cnthctl_el2, x0

	msr	cntvoff_el2, xzr		// Clear virtual offset



#ifdef CONFIG_ARM_GIC_V3

	/* GICv3 system register access */

	mrs	x0, id_aa64pfr0_el1

	ubfx	x0, x0, #24, #4

	cmp	x0, #1

	b.ne	3f



	mrs	x0, ICC_SRE_EL2

	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1

	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1

	msr	ICC_SRE_EL2, x0

	isb					// Make sure SRE is now set

	msr	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults



3:

#endif



	/* Populate ID registers. */

	mrs	x0, midr_el1

	mrs	x1, mpidr_el1

arch/arm64/kernel/hyp-stub.S

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 


#include <linux/init.h>

#include <linux/linkage.h>

#include <linux/irqchip/arm-gic-v3.h>



#include <asm/assembler.h>

#include <asm/ptrace.h>

drivers/irqchip/Kconfig

+19 −0
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ config ARM_GIC 
config GIC_NON_BANKED

	bool



config ARM_GIC_V3

	bool

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER



config ARM_NVIC

	bool

	select IRQ_DOMAIN
@@ -30,6 +35,20 @@ config ARM_VIC_NR 
	  The maximum number of VICs available in the system, for

	  power management.



config ATMEL_AIC_IRQ

	bool

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ



config ATMEL_AIC5_IRQ

	bool

	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ



config BRCMSTB_L2_IRQ

	bool

	depends on ARM