Commit 1aa8e847 authored by Sujith's avatar Sujith Committed by John W. Linville
Browse files

ath9k: Remove has_hw_phycounters 



PHY counters are available in all chipsets supported
by ath9k. Remove the check.

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 2a219eb2

drivers/net/wireless/ath/ath9k/ani.c

+87 −108
Original line number Diff line number Diff line
@@ -236,9 +236,8 @@ static void ath9k_ani_restart(struct ath_hw *ah) 
		return;



	aniState = ah->curani;



	aniState->listenTime = 0;

	if (ah->has_hw_phycounters) {



	if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {

		aniState->ofdmPhyErrBase = 0;

		DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -265,7 +264,7 @@ static void ath9k_ani_restart(struct ath_hw *ah) 
	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);



	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);

	}



	aniState->ofdmPhyErrCount = 0;

	aniState->cckPhyErrCount = 0;

}
@@ -530,18 +529,12 @@ void ath9k_ani_reset(struct ath_hw *ah) 
	if (aniState->firstepLevel != 0)

		ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,

				     aniState->firstepLevel);

	if (ah->has_hw_phycounters) {



	ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &

			     ~ATH9K_RX_FILTER_PHYERR);

	ath9k_ani_restart(ah);

	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);



	} else {

		ath9k_ani_restart(ah);

		ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |

				     ATH9K_RX_FILTER_PHYERR);

	}

}



void ath9k_hw_ani_monitor(struct ath_hw *ah,
@@ -550,6 +543,8 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 
{

	struct ar5416AniState *aniState;

	int32_t listenTime;

	u32 phyCnt1, phyCnt2;

	u32 ofdmPhyErrCnt, cckPhyErrCnt;



	if (!DO_ANI(ah))

		return;
@@ -566,10 +561,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 


	aniState->listenTime += listenTime;



	if (ah->has_hw_phycounters) {

		u32 phyCnt1, phyCnt2;

		u32 ofdmPhyErrCnt, cckPhyErrCnt;



	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);



	phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
@@ -609,7 +600,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 
	ah->stats.ast_ani_cckerrs +=

		cckPhyErrCnt - aniState->cckPhyErrCount;

	aniState->cckPhyErrCount = cckPhyErrCnt;

	}



	if (aniState->listenTime > 5 * ah->aniperiod) {

		if (aniState->ofdmPhyErrCount <= aniState->listenTime *
@@ -632,11 +622,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, 
	}

}



bool ath9k_hw_phycounters(struct ath_hw *ah)

{

	return ah->has_hw_phycounters ? true : false;

}



void ath9k_enable_mib_counters(struct ath_hw *ah)

{

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
@@ -781,9 +766,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
{

	int i;



	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");



	ah->has_hw_phycounters = 1;

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n");



	memset(ah->ani, 0, sizeof(ah->ani));

	for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -799,14 +782,12 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
			ATH9K_ANI_CCK_WEAK_SIG_THR;

		ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;

		ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;

		if (ah->has_hw_phycounters) {

		ah->ani[i].ofdmPhyErrBase =

			AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;

		ah->ani[i].cckPhyErrBase =

			AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;

	}

	}

	if (ah->has_hw_phycounters) {



	DPRINTF(ah->ah_sc, ATH_DBG_ANI,

		"Setting OfdmErrBase = 0x%08x\n",

		ah->ani[0].ofdmPhyErrBase);
@@ -816,7 +797,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
	REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);

	REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);

	ath9k_enable_mib_counters(ah);

	}



	ah->aniperiod = ATH9K_ANI_PERIOD;

	if (ah->config.enable_ani)

		ah->proc_phyerr |= HAL_PROCESS_ANI;
@@ -826,9 +807,7 @@ void ath9k_hw_ani_disable(struct ath_hw *ah) 
{

	DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n");



	if (ah->has_hw_phycounters) {

	ath9k_hw_disable_mib_counters(ah);

	REG_WRITE(ah, AR_PHY_ERR_1, 0);

	REG_WRITE(ah, AR_PHY_ERR_2, 0);

}
 
}

drivers/net/wireless/ath/ath9k/ani.h

+0 −1
Original line number Diff line number Diff line
@@ -124,7 +124,6 @@ void ath9k_ani_reset(struct ath_hw *ah); 
void ath9k_hw_ani_monitor(struct ath_hw *ah,

			  const struct ath9k_node_stats *stats,

			  struct ath9k_channel *chan);

bool ath9k_hw_phycounters(struct ath_hw *ah);

void ath9k_enable_mib_counters(struct ath_hw *ah);

void ath9k_hw_disable_mib_counters(struct ath_hw *ah);

u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,

drivers/net/wireless/ath/ath9k/hw.h

+0 −1
Original line number Diff line number Diff line
@@ -507,7 +507,6 @@ struct ath_hw { 


	/* ANI */

	u32 proc_phyerr;

	bool has_hw_phycounters;

	u32 aniperiod;

	struct ar5416AniState *curani;

	struct ar5416AniState ani[255];

drivers/net/wireless/ath/ath9k/main.c

+1 −2
Original line number Diff line number Diff line
@@ -2214,7 +2214,6 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, 
	if ((conf->type == NL80211_IFTYPE_STATION) ||

	    (conf->type == NL80211_IFTYPE_ADHOC) ||

	    (conf->type == NL80211_IFTYPE_MESH_POINT)) {

		if (ath9k_hw_phycounters(sc->sc_ah))

		sc->imask |= ATH9K_INT_MIB;

		sc->imask |= ATH9K_INT_TSFOOR;

	}