Commit 1a944729 authored by Codrin Ciubotariu's avatar Codrin Ciubotariu Committed by Nicolas Ferre
Browse files

clk: at91: sama7g5: fix parents of PDMCs' GCLK 



Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: cb783bbb ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: default avatarCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
parent a5ab04af

drivers/clk/at91/sama7g5.c

+4 −4
Original line number Diff line number Diff line
@@ -699,16 +699,16 @@ static const struct { 
	{ .n  = "pdmc0_gclk",

	  .id = 68,

	  .r = { .max = 50000000  },

	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },

	  .pp_mux_table = { 5, 8, },

	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },

	  .pp_mux_table = { 5, 9, },

	  .pp_count = 2,

	  .pp_chg_id = INT_MIN, },



	{ .n  = "pdmc1_gclk",

	  .id = 69,

	  .r = { .max = 50000000, },

	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },

	  .pp_mux_table = { 5, 8, },

	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },

	  .pp_mux_table = { 5, 9, },

	  .pp_count = 2,

	  .pp_chg_id = INT_MIN, },