Unverified Commit 1a4cf058 authored by Javier Martinez Canillas's avatar Javier Martinez Canillas
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drm/panel-xinpeng-xpp055c272: Drop custom DSI write macro 



There is a macro for this already in the <drm/drm_mipi_dsi.h> header, use
that instead and delete the custom DSI write macro defined in the driver.

Signed-off-by: default avatarJavier Martinez Canillas <javierm@redhat.com>
Reviewed-by: default avatarSam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230107191822.3787147-14-javierm@redhat.com
parent 7b00536a

drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c

+52 −60
Original line number Diff line number Diff line
@@ -60,14 +60,6 @@ static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel) 
	return container_of(panel, struct xpp055c272, panel);

}



#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\

		static const u8 b[] = { cmd, seq };			\

		int ret;						\

		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\

		if (ret < 0)						\

			return ret;					\

	} while (0)



static int xpp055c272_init_sequence(struct xpp055c272 *ctx)

{

	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
@@ -77,37 +69,37 @@ static int xpp055c272_init_sequence(struct xpp055c272 *ctx) 
	 * Init sequence was supplied by the panel vendor without much

	 * documentation.

	 */

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETMIPI,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI,

			       0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00,

			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,

			       0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01,

			       0x00, 0x00, 0x37);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETRGBIF,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER_EXT, 0x25);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF,

			       0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00,

			       0x00, 0x00);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETSCR,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR,

			       0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,

			       0x00);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETEQ,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ,

			       0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,

			       0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETPOWER,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER,

			       0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd,

			       0x67, 0x77, 0x33, 0x33);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETECO, 0x00, 0x00, 0xff,

			       0xff, 0x01, 0xff);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETBGP, 0x09, 0x09);

	msleep(20);



	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP1,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVCOM, 0x87, 0x95);

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1,

			       0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12,

			       0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18,

			       0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80,
@@ -116,7 +108,7 @@ static int xpp055c272_init_sequence(struct xpp055c272 *ctx) 
			       0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88,

			       0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,

			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGIP2,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2,

			       0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,

			       0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35,

			       0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f,
@@ -125,7 +117,7 @@ static int xpp055c272_init_sequence(struct xpp055c272 *ctx) 
			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

			       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05,

			       0xa0, 0x00, 0x00, 0x00, 0x00);

	dsi_generic_write_seq(dsi, XPP055C272_CMD_SETGAMMA,

	mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGAMMA,

			       0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36,

			       0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11,

			       0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38,