Commit 1a4ae6d6 authored by Yazen Ghannam's avatar Yazen Ghannam Committed by PvsNarasimha
Browse files

EDAC/amd64: Rename debug_display_dimm_sizes() 

mainline inclusion
from mainline-v6.4-rc1
commit 00e4feb8
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAU6ZD

Reference: https://github.com/torvalds/linux/commit/00e4feb8c0476bbde3c8bf4a593e0f82ca9a4df6



--------------------------------

commit 00e4feb8 upstream

Use the "dct" and "umc" prefixes for legacy and modern versions
respectively.

Also, move the "dct" version to avoid a forward declaration, and fixup
some checkpatch warnings in the process.

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-7-yazen.ghannam@amd.com


Signed-off-by: default avatarHemanth Selam <Hemanth.Selam@amd.com>
Signed-off-by: default avatarPvsNarasimha <PVS.NarasimhaRao@amd.com>
parent 82ed1b6b

drivers/edac/amd64_edac.c

+63 −65
Original line number Diff line number Diff line
@@ -1019,7 +1019,65 @@ static unsigned long determine_edac_cap(struct amd64_pvt *pvt) 
	return edac_cap;

}



static void debug_display_dimm_sizes(struct amd64_pvt *, u8);

/*

 * debug routine to display the memory sizes of all logical DIMMs and its

 * CSROWs

 */

static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)

{

	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;

	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;

	int dimm, size0, size1;



	if (pvt->fam == 0xf) {

		/* K8 families < revF not supported yet */

		if (pvt->ext_model < K8_REV_F)

			return;



		WARN_ON(ctrl != 0);

	}



	if (pvt->fam == 0x10) {

		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1

							   : pvt->dbam0;

		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?

				 pvt->csels[1].csbases :

				 pvt->csels[0].csbases;

	} else if (ctrl) {

		dbam = pvt->dbam0;

		dcsb = pvt->csels[1].csbases;

	}

	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",

		 ctrl, dbam);



	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);



	/* Dump memory sizes for DIMM and its CSROWs */

	for (dimm = 0; dimm < 4; dimm++) {

		size0 = 0;

		if (dcsb[dimm * 2] & DCSB_CS_ENABLE)

			/*

			 * For F15m60h, we need multiplier for LRDIMM cs_size

			 * calculation. We pass dimm value to the dbam_to_cs

			 * mapper so we can find the multiplier from the

			 * corresponding DCSM.

			 */

			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,

						     DBAM_DIMM(dimm, dbam),

						     dimm);



		size1 = 0;

		if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE)

			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,

						     DBAM_DIMM(dimm, dbam),

						     dimm);



		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",

			   dimm * 2,     size0,

			   dimm * 2 + 1, size1);

	}

}





static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)

{
@@ -1094,7 +1152,7 @@ static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) 
	return cs_mode;

}



static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)

static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)

{

	int dimm, size0, size1, cs0, cs1, cs_mode;
@@ -1157,7 +1215,7 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) 
					i, 1 << ((tmp >> 4) & 0x3));

		}



		debug_display_dimm_sizes_df(pvt, i);

		umc_debug_display_dimm_sizes(pvt, i);

	}

}
@@ -1182,13 +1240,13 @@ static void __dump_misc_regs(struct amd64_pvt *pvt) 
		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)

				   : f10_dhar_offset(pvt));



	debug_display_dimm_sizes(pvt, 0);

	dct_debug_display_dimm_sizes(pvt, 0);



	/* everything below this point is Fam10h and above */

	if (pvt->fam == 0xf)

		return;



	debug_display_dimm_sizes(pvt, 1);

	dct_debug_display_dimm_sizes(pvt, 1);



	/* Only if NOT ganged does dclr1 have valid info */

	if (!dct_ganging_enabled(pvt))
@@ -2419,66 +2477,6 @@ static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, 
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);

}



/*

 * debug routine to display the memory sizes of all logical DIMMs and its

 * CSROWs

 */

static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)

{

	int dimm, size0, size1;

	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;

	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;



	if (pvt->fam == 0xf) {

		/* K8 families < revF not supported yet */

	       if (pvt->ext_model < K8_REV_F)

			return;

	       else

		       WARN_ON(ctrl != 0);

	}



	if (pvt->fam == 0x10) {

		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1

							   : pvt->dbam0;

		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?

				 pvt->csels[1].csbases :

				 pvt->csels[0].csbases;

	} else if (ctrl) {

		dbam = pvt->dbam0;

		dcsb = pvt->csels[1].csbases;

	}

	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",

		 ctrl, dbam);



	edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);



	/* Dump memory sizes for DIMM and its CSROWs */

	for (dimm = 0; dimm < 4; dimm++) {



		size0 = 0;

		if (dcsb[dimm*2] & DCSB_CS_ENABLE)

			/*

			 * For F15m60h, we need multiplier for LRDIMM cs_size

			 * calculation. We pass dimm value to the dbam_to_cs

			 * mapper so we can find the multiplier from the

			 * corresponding DCSM.

			 */

			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,

						     DBAM_DIMM(dimm, dbam),

						     dimm);



		size1 = 0;

		if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)

			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,

						     DBAM_DIMM(dimm, dbam),

						     dimm);



		amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",

				dimm * 2,     size0,

				dimm * 2 + 1, size1);

	}

}



static struct amd64_family_type family_types[] = {

	[K8_CPUS] = {

		.ctl_name = "K8",