Unverified Commit 1a0e5dbd authored by Vincent Chen's avatar Vincent Chen Committed by Palmer Dabbelt
Browse files

riscv: sifive: Add SiFive alternative ports 



Add required ports of the Alternative scheme for SiFive.

Signed-off-by: default avatarVincent Chen <vincent.chen@sifive.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 6f4eea90

arch/riscv/Kconfig.erratas

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@@ -9,4 +9,14 @@ config RISCV_ERRATA_ALTERNATIVE 
	  code patching is performed once in the boot stages. It means

	  that the overhead from this mechanism is just taken once.



config ERRATA_SIFIVE

	bool "SiFive errata"

	depends on RISCV_ERRATA_ALTERNATIVE

	help

	  All SiFive errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all SiFive errata. Please say "Y"

	  here if your platform uses SiFive CPU cores.



	  Otherwise, please say "N" here to avoid unnecessary overhead.



endmenu

arch/riscv/Kconfig.socs

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@@ -7,6 +7,7 @@ config SOC_SIFIVE 
	select CLK_SIFIVE

	select CLK_SIFIVE_PRCI

	select SIFIVE_PLIC

	select ERRATA_SIFIVE

	help

	  This enables support for SiFive SoC platform hardware.

arch/riscv/errata/Makefile

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obj-y	+= alternative.o

obj-$(CONFIG_ERRATA_SIFIVE) += sifive/

arch/riscv/errata/alternative.c

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@@ -42,6 +42,11 @@ static void __init init_alternative(void) 
	riscv_fill_cpu_mfr_info();



	switch (cpu_mfr_info.vendor_id) {

#ifdef CONFIG_ERRATA_SIFIVE

	case SIFIVE_VENDOR_ID:

		vendor_patch_func = sifive_errata_patch_func;

		break;

#endif

	default:

		vendor_patch_func = NULL;

	}

arch/riscv/errata/sifive/Makefile

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obj-y += errata.o