Commit 19fd04fb authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: Add usb nodes 



SM8450 features a single USB controller which connects to both HS and SS
phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC.

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211216110813.658384-1-vkoul@kernel.org
parent bf0a257a

arch/arm64/boot/dts/qcom/sm8450.dtsi

+89 −0
Original line number Diff line number Diff line
@@ -626,6 +626,52 @@ 
			#hwlock-cells = <1>;

		};



		usb_1_hsphy: phy@88e3000 {

			compatible = "qcom,sm8450-usb-hs-phy",

				     "qcom,usb-snps-hs-7nm-phy";

			reg = <0 0x088e3000 0 0x400>;

			status = "disabled";

			#phy-cells = <0>;



			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "ref";



			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		};



		usb_1_qmpphy: phy-wrapper@88e9000 {

			compatible = "qcom,sm8450-qmp-usb3-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x20>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "ref_clk_src", "com_aux";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#phy-cells = <0>;

				#clock-cells = <1>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8450-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
@@ -1013,6 +1059,49 @@ 
				#clock-cells = <0>;

			};

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sm8450-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,

				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;

			clock-names = "cfg_noc", "core", "iface", "mock_utmi",

				      "sleep";



			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;

			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "dm_hs_phy_irq", "ss_phy_irq";



			power-domains = <&gcc USB30_PRIM_GDSC>;



			resets = <&gcc GCC_USB30_PRIM_BCR>;



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a600000 0 0xcd00>;

				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

				iommus = <&apps_smmu 0x0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

			};

		};

	};



	timer {