Commit 19a6b66c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix to match the CSR ASID masking rules when passing ASIDs to
   firmware

 - Force GCC to use ISA 2.2, to avoid a host of compatibily issues
   between toolchains

* tag 'riscv-for-linus-6.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Handle zicsr/zifencei issues between clang and binutils
  riscv: mm: Fix incorrect ASID argument when flushing TLB
parents 24956974 e89c2e81

arch/riscv/Kconfig

+22 −0
Original line number Diff line number Diff line
@@ -464,6 +464,28 @@ config TOOLCHAIN_HAS_ZIHINTPAUSE 
	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zihintpause)

	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23600



config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI

	def_bool y

	# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc

	depends on AS_IS_GNU && AS_VERSION >= 23800

	help

	  Newer binutils versions default to ISA spec version 20191213 which

	  moves some instructions from the I extension to the Zicsr and Zifencei

	  extensions.



config TOOLCHAIN_NEEDS_OLD_ISA_SPEC

	def_bool y

	depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI

	# https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16

	depends on CC_IS_CLANG && CLANG_VERSION < 170000

	help

	  Certain versions of clang do not support zicsr and zifencei via -march

	  but newer versions of binutils require it for the reasons noted in the

	  help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This

	  option causes an older ISA spec compatible with these older versions

	  of clang to be passed to GAS, which has the same result as passing zicsr

	  and zifencei to -march.



config FPU

	bool "FPU support"

	default y

arch/riscv/Makefile

+6 −4
Original line number Diff line number Diff line
@@ -57,10 +57,12 @@ riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima 
riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd

riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c



# Newer binutils versions default to ISA spec version 20191213 which moves some

# instructions from the I extension to the Zicsr and Zifencei extensions.

toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)

riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei

ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC

KBUILD_CFLAGS += -Wa,-misa-spec=2.2

KBUILD_AFLAGS += -Wa,-misa-spec=2.2

else

riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei

endif



# Check if the toolchain supports Zihintpause extension

riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause

arch/riscv/include/asm/tlbflush.h

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include <asm/errata_list.h>



#ifdef CONFIG_MMU

extern unsigned long asid_mask;



static inline void local_flush_tlb_all(void)

{

	__asm__ __volatile__ ("sfence.vma" : : : "memory");

arch/riscv/mm/context.c

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); 


static unsigned long asid_bits;

static unsigned long num_asids;

static unsigned long asid_mask;

unsigned long asid_mask;



static atomic_long_t current_version;

arch/riscv/mm/tlbflush.c

+1 −1
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, 
	/* check if the tlbflush needs to be sent to other CPUs */

	broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;

	if (static_branch_unlikely(&use_asid_allocator)) {

		unsigned long asid = atomic_long_read(&mm->context.id);

		unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask;



		if (broadcast) {

			sbi_remote_sfence_vma_asid(cmask, start, size, asid);