Commit 193e5e1d authored by Junxin Chen's avatar Junxin Chen Committed by Fengyan
Browse files

UNIC: add nfe ras for PFA and TXPM module 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I850RQ


CVE: NA

-----------------------------------------------------

This patch supports the dealing process of ras for PFA
and TXPM two modules. Firstly, we add PFA and TXPM module
for ras parser to support UB version. Next, we add the nfe
error checking of ras in driver process for PFA and TXPM.

Signed-off-by: default avatarJunxin Chen <chenjunxin1@huawei.com>
parent 41edd9ef

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include "hclge_main.h"

#include "hclge_regs.h"

#include "hclge_tm.h"

#include "hclge_udma.h"

#include "hnae3.h"



static const char * const state_str[] = { "off", "on" };
@@ -1814,6 +1815,8 @@ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len) 
				 hclge_read_dev(&hdev->hw, offset));

	}



	hclge_dbg_dump_udma_rst_info(hdev, buf, len, &pos);



	pos += scnprintf(buf + pos, len - pos, "hdev state: 0x%lx\n",

			 hdev->state);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

+11 −2
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
/* Copyright (c) 2016-2017 Hisilicon Limited. */



#include "hclge_err.h"

#include "hclge_udma.h"



static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {

	{
@@ -1245,6 +1246,12 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = { 
	}, {

		.module_id = MODULE_HIMAC,

		.msg = "MODULE_HIMAC"

	}, {

		.module_id = MODULE_PFA,

		.msg = "MODULE_PFA"

	}, {

		.module_id = MODULE_TXPM,

		.msg = "MODULE_TXPM"

	}, {

		.module_id = MODULE_ROCEE_TOP,

		.msg = "MODULE_ROCEE_TOP"
@@ -2751,7 +2758,7 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev) 


bool hclge_find_error_source(struct hclge_dev *hdev)

{

	u32 msix_src_flag, hw_err_src_flag;

	u32 msix_src_flag, hw_err_src_flag, udma_err_src_flag;



	msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &

			HCLGE_VECTOR0_REG_MSIX_MASK;
@@ -2759,8 +2766,10 @@ bool hclge_find_error_source(struct hclge_dev *hdev) 
	hw_err_src_flag = hclge_read_dev(&hdev->hw,

					 HCLGE_RAS_PF_OTHER_INT_STS_REG) &

			  HCLGE_RAS_REG_ERR_MASK;

	udma_err_src_flag = hclge_get_udma_error_reg(hdev) &

			   HCLGE_RAS_REG_ERR_MASK_UB;



	return msix_src_flag || hw_err_src_flag;

	return msix_src_flag || hw_err_src_flag || udma_err_src_flag;

}



void hclge_handle_occurred_error(struct hclge_dev *hdev)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

+2 −0
Original line number Diff line number Diff line
@@ -141,6 +141,8 @@ enum hclge_mod_name_list { 
	MODULE_TXDMA		= 13,

	MODULE_MASTER		= 14,

	MODULE_HIMAC		= 15,

	MODULE_PFA		= 16,

	MODULE_TXPM		= 17,

	/* add new MODULE NAME for NIC here in order */

	MODULE_ROCEE_TOP	= 40,

	MODULE_ROCEE_TIMER	= 41,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+7 −4
Original line number Diff line number Diff line
@@ -3427,13 +3427,14 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 


static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)

{

	u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;

	u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg, udma_err_src_reg;



	/* fetch the events from their corresponding regs */

	cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);

	msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);

	hw_err_src_reg = hclge_read_dev(&hdev->hw,

					HCLGE_RAS_PF_OTHER_INT_STS_REG);

	udma_err_src_reg = hclge_get_udma_error_reg(hdev);



	/* Assumption: If by any chance reset and mailbox events are reported

	 * together then we will only process reset event in this go and will
@@ -3463,7 +3464,8 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 


	/* check for vector0 msix event and hardware error event source */

	if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||

	    hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)

	    hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK ||

	    udma_err_src_reg & HCLGE_RAS_REG_ERR_MASK_UB)

		return HCLGE_VECTOR0_EVENT_ERR;



	/* check for vector0 ptp event source */
@@ -3481,8 +3483,9 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 


	/* print other vector0 event source */

	dev_info(&hdev->pdev->dev,

		 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",

		 cmdq_src_reg, hw_err_src_reg, msix_src_reg);

		 "INT status: CMDQ(%#x) HW errors(%#x, %#x) other(%#x)\n",

		 cmdq_src_reg, hw_err_src_reg, udma_err_src_reg,

		 msix_src_reg);



	return HCLGE_VECTOR0_EVENT_OTHER;

}

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_udma.c

+33 −0
Original line number Diff line number Diff line
@@ -16,6 +16,11 @@ 
#include "hclge_main.h"

#include "hclge_udma.h"

#include "hclge_err.h"

#include "hclge_debugfs.h"



static const struct hclge_dbg_status_dfx_info hclge_dbg_rst_info_ub[] = {

	{HCLGE_RAS_PF_OTHER_INT_STS_REG_UB, "UB RAS interrupt status"}

};



static int hclge_init_udma_base_info(struct hclge_vport *vport)

{
@@ -104,3 +109,31 @@ int hclge_init_udma_client_instance(struct hnae3_ae_dev *ae_dev, 


	return ret;

}



u32 hclge_get_udma_error_reg(struct hclge_dev *hdev)

{

	u32 hw_err_src_reg = 0;



	if (hnae3_dev_ubl_supported(hdev->ae_dev) ||

	    hnae3_dev_udma_supported(hdev->ae_dev))

		hw_err_src_reg = hclge_read_dev(&hdev->hw,

						HCLGE_RAS_PF_OTHER_INT_STS_REG_UB);



	return hw_err_src_reg;

}



void hclge_dbg_dump_udma_rst_info(struct hclge_dev *hdev, char *buf, int len,

				  int *pos)

{

	u32 i, offset;



	if (hnae3_dev_ubl_supported(hdev->ae_dev) ||

	    hnae3_dev_udma_supported(hdev->ae_dev)) {

		for (i = 0; i < ARRAY_SIZE(hclge_dbg_rst_info_ub); i++) {

			offset = hclge_dbg_rst_info_ub[i].offset;

			*pos += scnprintf(buf + *pos, len - *pos, "%s: 0x%x\n",

					  hclge_dbg_rst_info_ub[i].message,

					  hclge_read_dev(&hdev->hw, offset));

		}

	}

}