Commit 1908a07c authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Select correct DTO source



[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.

Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cbd3e844
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+27 −0
Original line number Diff line number Diff line
@@ -992,7 +992,18 @@ static bool dcn31_program_pix_clk(
			REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
			REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
		}
#if defined(CONFIG_DRM_AMD_DC_DCN)
		/* Enable DTO */
		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
			REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
					DP_DTO0_ENABLE, 1,
					PIPE0_DTO_SRC_SEL, 1);
		else
			REG_UPDATE(PIXEL_RATE_CNTL[inst],
					DP_DTO0_ENABLE, 1);
#else
		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
#endif
	} else {
		if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
			unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
@@ -1004,10 +1015,26 @@ static bool dcn31_program_pix_clk(
			REG_WRITE(MODULO[inst], dp_dto_ref_100hz);

			/* Enable DTO */
	#if defined(CONFIG_DRM_AMD_DC_DCN)
			if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
				REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
						DP_DTO0_ENABLE, 1,
						PIPE0_DTO_SRC_SEL, 1);
			else
				REG_UPDATE(PIXEL_RATE_CNTL[inst],
						DP_DTO0_ENABLE, 1);
	#else
			REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
	#endif
			return true;
		}

#if defined(CONFIG_DRM_AMD_DC_DCN)
		if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
			REG_UPDATE(PIXEL_RATE_CNTL[inst],
					PIPE0_DTO_SRC_SEL, 0);
#endif

		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
		bp_pc_params.controller_id = pix_clk_params->controller_id;
		bp_pc_params.pll_id = clock_source->id;