Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +2 −0 Original line number Diff line number Diff line Loading @@ -1430,6 +1430,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) grctx->r418800(gr); if (grctx->r419eb0) grctx->r419eb0(gr); if (grctx->r419e00) grctx->r419e00(gr); } #define CB_RESERVED 0x80000 Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ struct gf100_grctx_func { void (*r419cb8)(struct gf100_gr *); void (*r418800)(struct gf100_gr *); void (*r419eb0)(struct gf100_gr *); void (*r419e00)(struct gf100_gr *); }; extern const struct gf100_grctx_func gf100_grctx; Loading drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +12 −4 Original line number Diff line number Diff line Loading @@ -860,6 +860,16 @@ gm107_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ static void gm107_grctx_generate_r419e00(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); } void gm107_grctx_generate_bundle(struct gf100_grctx *info) { Loading Loading @@ -971,10 +981,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); grctx->r419e00(gr); } const struct gf100_grctx_func Loading Loading @@ -1006,4 +1013,5 @@ gm107_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .r406500 = gm107_grctx_generate_r406500, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419e00 = gm107_grctx_generate_r419e00, }; Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +2 −0 Original line number Diff line number Diff line Loading @@ -1430,6 +1430,8 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) grctx->r418800(gr); if (grctx->r419eb0) grctx->r419eb0(gr); if (grctx->r419e00) grctx->r419e00(gr); } #define CB_RESERVED 0x80000 Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +1 −0 Original line number Diff line number Diff line Loading @@ -67,6 +67,7 @@ struct gf100_grctx_func { void (*r419cb8)(struct gf100_gr *); void (*r418800)(struct gf100_gr *); void (*r419eb0)(struct gf100_gr *); void (*r419e00)(struct gf100_gr *); }; extern const struct gf100_grctx_func gf100_grctx; Loading
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +12 −4 Original line number Diff line number Diff line Loading @@ -860,6 +860,16 @@ gm107_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ static void gm107_grctx_generate_r419e00(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); } void gm107_grctx_generate_bundle(struct gf100_grctx *info) { Loading Loading @@ -971,10 +981,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); grctx->r419e00(gr); } const struct gf100_grctx_func Loading Loading @@ -1006,4 +1013,5 @@ gm107_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .r406500 = gm107_grctx_generate_r406500, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419e00 = gm107_grctx_generate_r419e00, };