Commit 18b3b7b3 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ixp4xx: Drop all common code 



After moving away from all the code we depend on in common we can
get a clean device tree boot and delete the common code in
arch/arm/mach-ixp4xx/common.c altogether.

Two physical register addresses remain in use, just copy these
verbatim into uncompress.h.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220211223238.648934-13-linus.walleij@linaro.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 00ba9357

arch/arm/mach-ixp4xx/Makefile

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# SPDX-License-Identifier: GPL-2.0

obj-y	+= ixp4xx-of.o common.o
 
obj-y	+= ixp4xx-of.o

arch/arm/mach-ixp4xx/common.c

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/*

 * arch/arm/mach-ixp4xx/common.c

 *

 * Generic code shared across all IXP4XX platforms

 *

 * Maintainer: Deepak Saxena <dsaxena@plexity.net>

 *

 * Copyright 2002 (c) Intel Corporation

 * Copyright 2003-2004 (c) MontaVista, Software, Inc. 

 * 

 * This file is licensed under  the terms of the GNU General Public 

 * License version 2. This program is licensed "as is" without any 

 * warranty of any kind, whether express or implied.

 */



#include <linux/kernel.h>

#include <linux/mm.h>

#include <linux/init.h>

#include <linux/serial.h>

#include <linux/tty.h>

#include <linux/platform_device.h>

#include <linux/serial_core.h>

#include <linux/interrupt.h>

#include <linux/bitops.h>

#include <linux/io.h>

#include <linux/export.h>

#include <linux/cpu.h>

#include <linux/pci.h>

#include <linux/sched_clock.h>

#include <linux/soc/ixp4xx/cpu.h>

#include <linux/irqchip/irq-ixp4xx.h>

#include <linux/platform_data/timer-ixp4xx.h>

#include <mach/hardware.h>

#include <linux/uaccess.h>

#include <asm/page.h>

#include <asm/exception.h>

#include <asm/irq.h>

#include <asm/system_misc.h>

#include <asm/mach/map.h>

#include <asm/mach/irq.h>

#include <asm/mach/time.h>



#include "irqs.h"



#define IXP4XX_TIMER_FREQ 66666000



/*************************************************************************

 * IXP4xx chipset I/O mapping

 *************************************************************************/

static struct map_desc ixp4xx_io_desc[] __initdata = {

	{	/* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */

		.virtual	= (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),

		.length		= IXP4XX_PERIPHERAL_REGION_SIZE,

		.type		= MT_DEVICE

	}, {	/* Expansion Bus Config Registers */

		.virtual	= (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),

		.length		= IXP4XX_EXP_CFG_REGION_SIZE,

		.type		= MT_DEVICE

	}, {	/* PCI Registers */

		.virtual	= (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),

		.length		= IXP4XX_PCI_CFG_REGION_SIZE,

		.type		= MT_DEVICE

	},

};



void __init ixp4xx_map_io(void)

{

  	iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));

}



void __init ixp4xx_init_irq(void)

{

	/*

	 * ixp4xx does not implement the XScale PWRMODE register

	 * so it must not call cpu_do_idle().

	 */

	cpu_idle_poll_ctrl(true);



	ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,

			(cpu_is_ixp46x() || cpu_is_ixp43x()));

}



void __init ixp4xx_timer_init(void)

{

	return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,

				  IRQ_IXP4XX_TIMER1,

				  IXP4XX_TIMER_FREQ);

}



static struct resource ixp4xx_udc_resources[] = {

	[0] = {

		.start  = 0xc800b000,

		.end    = 0xc800bfff,

		.flags  = IORESOURCE_MEM,

	},

	[1] = {

		.start  = IRQ_IXP4XX_USB,

		.end    = IRQ_IXP4XX_USB,

		.flags  = IORESOURCE_IRQ,

	},

};



static struct resource ixp4xx_gpio_resource[] = {

	{

		.start = IXP4XX_GPIO_BASE_PHYS,

		.end = IXP4XX_GPIO_BASE_PHYS + 0xfff,

		.flags = IORESOURCE_MEM,

	},

};



static struct platform_device ixp4xx_gpio_device = {

	.name           = "ixp4xx-gpio",

	.id             = -1,

	.dev = {

		.coherent_dma_mask      = DMA_BIT_MASK(32),

	},

	.resource = ixp4xx_gpio_resource,

	.num_resources  = ARRAY_SIZE(ixp4xx_gpio_resource),

};



/*

 * USB device controller. The IXP4xx uses the same controller as PXA25X,

 * so we just use the same device.

 */

static struct platform_device ixp4xx_udc_device = {

	.name           = "pxa25x-udc",

	.id             = -1,

	.num_resources  = 2,

	.resource       = ixp4xx_udc_resources,

};



static struct resource ixp4xx_npe_resources[] = {

	{

		.start = IXP4XX_NPEA_BASE_PHYS,

		.end = IXP4XX_NPEA_BASE_PHYS + 0xfff,

		.flags = IORESOURCE_MEM,

	},

	{

		.start = IXP4XX_NPEB_BASE_PHYS,

		.end = IXP4XX_NPEB_BASE_PHYS + 0xfff,

		.flags = IORESOURCE_MEM,

	},

	{

		.start = IXP4XX_NPEC_BASE_PHYS,

		.end = IXP4XX_NPEC_BASE_PHYS + 0xfff,

		.flags = IORESOURCE_MEM,

	},



};



static struct platform_device ixp4xx_npe_device = {

	.name           = "ixp4xx-npe",

	.id             = -1,

	.num_resources  = ARRAY_SIZE(ixp4xx_npe_resources),

	.resource       = ixp4xx_npe_resources,

};



static struct resource ixp4xx_qmgr_resources[] = {

	{

		.start = IXP4XX_QMGR_BASE_PHYS,

		.end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,

		.flags = IORESOURCE_MEM,

	},

	{

		.start = IRQ_IXP4XX_QM1,

		.end = IRQ_IXP4XX_QM1,

		.flags = IORESOURCE_IRQ,

	},

	{

		.start = IRQ_IXP4XX_QM2,

		.end = IRQ_IXP4XX_QM2,

		.flags = IORESOURCE_IRQ,

	},

};



static struct platform_device ixp4xx_qmgr_device = {

	.name           = "ixp4xx-qmgr",

	.id             = -1,

	.num_resources  = ARRAY_SIZE(ixp4xx_qmgr_resources),

	.resource       = ixp4xx_qmgr_resources,

};



static struct platform_device *ixp4xx_devices[] __initdata = {

	&ixp4xx_npe_device,

	&ixp4xx_qmgr_device,

	&ixp4xx_gpio_device,

	&ixp4xx_udc_device,

};



static struct resource ixp46x_i2c_resources[] = {

	[0] = {

		.start 	= 0xc8011000,

		.end	= 0xc801101c,

		.flags	= IORESOURCE_MEM,

	},

	[1] = {

		.start 	= IRQ_IXP4XX_I2C,

		.end	= IRQ_IXP4XX_I2C,

		.flags	= IORESOURCE_IRQ

	}

};



/* A single 32-bit register on IXP46x */

#define IXP4XX_HWRANDOM_BASE_PHYS	0x70002100



static struct resource ixp46x_hwrandom_resource[] = {

	{

		.start = IXP4XX_HWRANDOM_BASE_PHYS,

		.end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,

		.flags = IORESOURCE_MEM,

	},

};



static struct platform_device ixp46x_hwrandom_device = {

	.name           = "ixp4xx-hwrandom",

	.id             = -1,

	.dev = {

		.coherent_dma_mask      = DMA_BIT_MASK(32),

	},

	.resource = ixp46x_hwrandom_resource,

	.num_resources  = ARRAY_SIZE(ixp46x_hwrandom_resource),

};



/*

 * I2C controller. The IXP46x uses the same block as the IOP3xx, so

 * we just use the same device name.

 */

static struct platform_device ixp46x_i2c_controller = {

	.name		= "IOP3xx-I2C",

	.id		= 0,

	.num_resources	= 2,

	.resource	= ixp46x_i2c_resources

};



static struct resource ixp46x_ptp_resources[] = {

	DEFINE_RES_MEM(IXP4XX_TIMESYNC_BASE_PHYS, SZ_4K),

	DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO8, "master"),

	DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO7, "slave"),

};



static struct platform_device ixp46x_ptp = {

	.name		= "ptp-ixp46x",

	.id		= -1,

	.resource	= ixp46x_ptp_resources,

	.num_resources	= ARRAY_SIZE(ixp46x_ptp_resources),

};



static struct platform_device *ixp46x_devices[] __initdata = {

	&ixp46x_hwrandom_device,

	&ixp46x_i2c_controller,

	&ixp46x_ptp,

};



unsigned long ixp4xx_exp_bus_size;

EXPORT_SYMBOL(ixp4xx_exp_bus_size);



static struct platform_device_info ixp_dev_info __initdata = {

	.name		= "ixp4xx_crypto",

	.id		= 0,

	.dma_mask	= DMA_BIT_MASK(32),

};



static int __init ixp_crypto_register(void)

{

	struct platform_device *pdev;



	if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |

				IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {

		printk(KERN_ERR "ixp_crypto: No HW crypto available\n");

		return -ENODEV;

	}



	pdev = platform_device_register_full(&ixp_dev_info);

	if (IS_ERR(pdev))

		return PTR_ERR(pdev);



	return 0;

}



void __init ixp4xx_sys_init(void)

{

	ixp4xx_exp_bus_size = SZ_16M;



	platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));



	if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX))

		ixp_crypto_register();



	if (cpu_is_ixp46x()) {

		int region;



		platform_add_devices(ixp46x_devices,

				ARRAY_SIZE(ixp46x_devices));



		for (region = 0; region < 7; region++) {

			if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {

				ixp4xx_exp_bus_size = SZ_32M;

				break;

			}

		}

	}



	printk("IXP4xx: Using %luMiB expansion bus window size\n",

			ixp4xx_exp_bus_size >> 20);

}



unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;

EXPORT_SYMBOL(ixp4xx_timer_freq);



void ixp4xx_restart(enum reboot_mode mode, const char *cmd)

{

	if (mode == REBOOT_SOFT) {

		/* Jump into ROM at address 0 */

		soft_restart(0);

	} else {

		/* Use on-chip reset capability */



		/* set the "key" register to enable access to

		 * "timer" and "enable" registers

		 */

		*IXP4XX_OSWK = IXP4XX_WDT_KEY;



		/* write 0 to the timer register for an immediate reset */

		*IXP4XX_OSWT = 0;



		*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;

	}

}

arch/arm/mach-ixp4xx/include/mach/hardware.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * arch/arm/mach-ixp4xx/include/mach/hardware.h 

 *

 * Copyright (C) 2002 Intel Corporation.

 * Copyright (C) 2003-2004 MontaVista Software, Inc.

 */



/*

 * Hardware definitions for IXP4xx based systems

 */



#ifndef __ASM_ARCH_HARDWARE_H__

#define __ASM_ARCH_HARDWARE_H__



/* Register locations and bits */

#include "ixp4xx-regs.h"



#ifndef __ASSEMBLER__

#include <linux/soc/ixp4xx/cpu.h>

#endif



/* Platform helper functions and definitions */

#include "platform.h"



#endif  /* _ASM_ARCH_HARDWARE_H */

arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

 *

 * Register definitions for IXP4xx chipset. This file contains 

 * register location and bit definitions only. Platform specific 

 * definitions and helper function declarations are in platform.h 

 * and machine-name.h.

 *

 * Copyright (C) 2002 Intel Corporation.

 * Copyright (C) 2003-2004 MontaVista Software, Inc.

 */



#ifndef _ASM_ARM_IXP4XX_H_

#define _ASM_ARM_IXP4XX_H_



/*

 * IXP4xx Linux Memory Map:

 *

 * Phy		Size		Virt		Description

 * =========================================================================

 *

 * 0x00000000	0x10000000(max)	PAGE_OFFSET	System RAM

 *

 * 0x48000000	0x04000000	ioremap'd	PCI Memory Space

 *

 * 0x50000000	0x10000000	ioremap'd	EXP BUS

 *

 * 0xC8000000	0x00013000	0xFEF00000	On-Chip Peripherals

 *

 * 0xC0000000	0x00001000	0xFEF13000	PCI CFG

 *

 * 0xC4000000	0x00001000	0xFEF14000	EXP CFG

 *

 * 0x60000000	0x00004000	0xFEF15000	QMgr

 */



/*

 * Queue Manager

 */

#define IXP4XX_QMGR_BASE_PHYS		0x60000000



/*

 * Peripheral space, including debug UART. Must be section-aligned so that

 * it can be used with the low-level debug code.

 */

#define IXP4XX_PERIPHERAL_BASE_PHYS	0xC8000000

#define IXP4XX_PERIPHERAL_BASE_VIRT	IOMEM(0xFEC00000)

#define IXP4XX_PERIPHERAL_REGION_SIZE	0x00013000



/*

 * PCI Config registers

 */

#define IXP4XX_PCI_CFG_BASE_PHYS	0xC0000000

#define IXP4XX_PCI_CFG_BASE_VIRT	IOMEM(0xFEC13000)

#define IXP4XX_PCI_CFG_REGION_SIZE	0x00001000



/*

 * Expansion BUS Configuration registers

 */

#define IXP4XX_EXP_CFG_BASE_PHYS	0xC4000000

#define IXP4XX_EXP_CFG_BASE_VIRT	0xFEC14000

#define IXP4XX_EXP_CFG_REGION_SIZE	0x00001000



#define IXP4XX_EXP_CS0_OFFSET	0x00

#define IXP4XX_EXP_CS1_OFFSET   0x04

#define IXP4XX_EXP_CS2_OFFSET   0x08

#define IXP4XX_EXP_CS3_OFFSET   0x0C

#define IXP4XX_EXP_CS4_OFFSET   0x10

#define IXP4XX_EXP_CS5_OFFSET   0x14

#define IXP4XX_EXP_CS6_OFFSET   0x18

#define IXP4XX_EXP_CS7_OFFSET   0x1C

#define IXP4XX_EXP_CFG0_OFFSET	0x20

#define IXP4XX_EXP_CFG1_OFFSET	0x24

#define IXP4XX_EXP_CFG2_OFFSET	0x28

#define IXP4XX_EXP_CFG3_OFFSET	0x2C



/*

 * Expansion Bus Controller registers.

 */

#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))



#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)

#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)

#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 

#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)

#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)

#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)

#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     

#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)



#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 

#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 

#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 

#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)





/*

 * Peripheral Space Register Region Base Addresses

 */

#define IXP4XX_UART1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)

#define IXP4XX_UART2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)

#define IXP4XX_PMU_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)

#define IXP4XX_INTC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)

#define IXP4XX_GPIO_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)

#define IXP4XX_TIMER_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)

#define IXP4XX_NPEA_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)

#define IXP4XX_NPEB_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)

#define IXP4XX_NPEC_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)

#define IXP4XX_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)

#define IXP4XX_EthC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)

#define IXP4XX_USB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)

/* ixp46X only */

#define IXP4XX_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)

#define IXP4XX_EthB1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)

#define IXP4XX_EthB2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)

#define IXP4XX_EthB3_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)

#define IXP4XX_TIMESYNC_BASE_PHYS	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)

#define IXP4XX_I2C_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)

#define IXP4XX_SSP_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)





/* The UART is explicitly put in the beginning of fixmap */

#define IXP4XX_UART1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)

#define IXP4XX_UART2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)

#define IXP4XX_PMU_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)

#define IXP4XX_INTC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)

#define IXP4XX_GPIO_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)

#define IXP4XX_TIMER_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)

#define IXP4XX_EthB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)

#define IXP4XX_EthC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)

#define IXP4XX_USB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)

/* ixp46X only */

#define IXP4XX_EthA_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)

#define IXP4XX_EthB1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)

#define IXP4XX_EthB2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)

#define IXP4XX_EthB3_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)

#define IXP4XX_TIMESYNC_BASE_VIRT	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)

#define IXP4XX_I2C_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)

#define IXP4XX_SSP_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)



/*

 * Constants to make it easy to access Timer Control/Status registers

 */

#define IXP4XX_OSTS_OFFSET	0x00  /* Continious TimeStamp */

#define IXP4XX_OST1_OFFSET	0x04  /* Timer 1 Timestamp */

#define IXP4XX_OSRT1_OFFSET	0x08  /* Timer 1 Reload */

#define IXP4XX_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */

#define IXP4XX_OSRT2_OFFSET	0x10  /* Timer 2 Reload */

#define IXP4XX_OSWT_OFFSET	0x14  /* Watchdog Timer */

#define IXP4XX_OSWE_OFFSET	0x18  /* Watchdog Enable */

#define IXP4XX_OSWK_OFFSET	0x1C  /* Watchdog Key */

#define IXP4XX_OSST_OFFSET	0x20  /* Timer Status */



/*

 * Operating System Timer Register Definitions.

 */



#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))



#define IXP4XX_OSTS	IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)

#define IXP4XX_OST1	IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)

#define IXP4XX_OSRT1	IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)

#define IXP4XX_OST2	IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)

#define IXP4XX_OSRT2	IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)

#define IXP4XX_OSWT	IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)

#define IXP4XX_OSWE	IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)

#define IXP4XX_OSWK	IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)

#define IXP4XX_OSST	IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)



/*

 * Timer register values and bit definitions 

 */

#define IXP4XX_OST_ENABLE		0x00000001

#define IXP4XX_OST_ONE_SHOT		0x00000002

/* Low order bits of reload value ignored */

#define IXP4XX_OST_RELOAD_MASK		0x00000003

#define IXP4XX_OST_DISABLED		0x00000000

#define IXP4XX_OSST_TIMER_1_PEND	0x00000001

#define IXP4XX_OSST_TIMER_2_PEND	0x00000002

#define IXP4XX_OSST_TIMER_TS_PEND	0x00000004

#define IXP4XX_OSST_TIMER_WDOG_PEND	0x00000008

#define IXP4XX_OSST_TIMER_WARM_RESET	0x00000010



#define	IXP4XX_WDT_KEY			0x0000482E



#define	IXP4XX_WDT_RESET_ENABLE		0x00000001

#define	IXP4XX_WDT_IRQ_ENABLE		0x00000002

#define	IXP4XX_WDT_COUNT_ENABLE		0x00000004





/*

 * Constants to make it easy to access PCI Control/Status registers

 */

#define PCI_NP_AD_OFFSET            0x00

#define PCI_NP_CBE_OFFSET           0x04

#define PCI_NP_WDATA_OFFSET         0x08

#define PCI_NP_RDATA_OFFSET         0x0c

#define PCI_CRP_AD_CBE_OFFSET       0x10

#define PCI_CRP_WDATA_OFFSET        0x14

#define PCI_CRP_RDATA_OFFSET        0x18

#define PCI_CSR_OFFSET              0x1c

#define PCI_ISR_OFFSET              0x20

#define PCI_INTEN_OFFSET            0x24

#define PCI_DMACTRL_OFFSET          0x28

#define PCI_AHBMEMBASE_OFFSET       0x2c

#define PCI_AHBIOBASE_OFFSET        0x30

#define PCI_PCIMEMBASE_OFFSET       0x34

#define PCI_AHBDOORBELL_OFFSET      0x38

#define PCI_PCIDOORBELL_OFFSET      0x3C

#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40

#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44

#define PCI_ATPDMA0_LENADDR_OFFSET  0x48

#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C

#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50

#define PCI_ATPDMA1_LENADDR_OFFSET	0x54



/*

 * PCI Control/Status Registers

 */

#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))



#define PCI_NP_AD               _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)

#define PCI_NP_CBE              _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)

#define PCI_NP_WDATA            _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)

#define PCI_NP_RDATA            _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)

#define PCI_CRP_AD_CBE          _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)

#define PCI_CRP_WDATA           _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)

#define PCI_CRP_RDATA           _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)

#define PCI_CSR                 _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 

#define PCI_ISR                 _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)

#define PCI_INTEN               _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)

#define PCI_DMACTRL             _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)

#define PCI_AHBMEMBASE          _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)

#define PCI_AHBIOBASE           _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)

#define PCI_PCIMEMBASE          _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)

#define PCI_AHBDOORBELL         _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)

#define PCI_PCIDOORBELL         _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)

#define PCI_ATPDMA0_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)

#define PCI_ATPDMA0_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)

#define PCI_ATPDMA0_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)

#define PCI_ATPDMA1_AHBADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)

#define PCI_ATPDMA1_PCIADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)

#define PCI_ATPDMA1_LENADDR     _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)



/*

 * PCI register values and bit definitions 

 */



/* CSR bit definitions */

#define PCI_CSR_HOST    	0x00000001

#define PCI_CSR_ARBEN   	0x00000002

#define PCI_CSR_ADS     	0x00000004

#define PCI_CSR_PDS     	0x00000008

#define PCI_CSR_ABE     	0x00000010

#define PCI_CSR_DBT     	0x00000020

#define PCI_CSR_ASE     	0x00000100

#define PCI_CSR_IC      	0x00008000



/* ISR (Interrupt status) Register bit definitions */

#define PCI_ISR_PSE     	0x00000001

#define PCI_ISR_PFE     	0x00000002

#define PCI_ISR_PPE     	0x00000004

#define PCI_ISR_AHBE    	0x00000008

#define PCI_ISR_APDC    	0x00000010

#define PCI_ISR_PADC    	0x00000020

#define PCI_ISR_ADB     	0x00000040

#define PCI_ISR_PDB     	0x00000080



/* INTEN (Interrupt Enable) Register bit definitions */

#define PCI_INTEN_PSE   	0x00000001

#define PCI_INTEN_PFE   	0x00000002

#define PCI_INTEN_PPE   	0x00000004

#define PCI_INTEN_AHBE  	0x00000008

#define PCI_INTEN_APDC  	0x00000010

#define PCI_INTEN_PADC  	0x00000020

#define PCI_INTEN_ADB   	0x00000040

#define PCI_INTEN_PDB   	0x00000080



/*

 * Shift value for byte enable on NP cmd/byte enable register

 */

#define IXP4XX_PCI_NP_CBE_BESL		4



/*

 * PCI commands supported by NP access unit

 */

#define NP_CMD_IOREAD			0x2

#define NP_CMD_IOWRITE			0x3

#define NP_CMD_CONFIGREAD		0xa

#define NP_CMD_CONFIGWRITE		0xb

#define NP_CMD_MEMREAD			0x6

#define	NP_CMD_MEMWRITE			0x7



/*

 * Constants for CRP access into local config space

 */

#define CRP_AD_CBE_BESL         20

#define CRP_AD_CBE_WRITE	0x00010000



#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */



#endif

arch/arm/mach-ixp4xx/include/mach/platform.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * arch/arm/mach-ixp4xx/include/mach/platform.h

 *

 * Constants and functions that are useful to IXP4xx platform-specific code

 * and device drivers.

 *

 * Copyright (C) 2004 MontaVista Software, Inc.

 */



#ifndef __ASM_ARCH_HARDWARE_H__

#error "Do not include this directly, instead #include <mach/hardware.h>"

#endif



#ifndef __ASSEMBLY__



#include <linux/reboot.h>

#include <linux/platform_data/eth_ixp4xx.h>



#include <asm/types.h>



#ifndef	__ARMEB__

#define	REG_OFFSET	0

#else

#define	REG_OFFSET	3

#endif



/*

 * Expansion bus memory regions

 */

#define IXP4XX_EXP_BUS_BASE_PHYS	(0x50000000)



/*

 * The expansion bus on the IXP4xx can be configured for either 16 or

 * 32MB windows and the CS offset for each region changes based on the

 * current configuration. This means that we cannot simply hardcode

 * each offset. ixp4xx_sys_init() looks at the expansion bus configuration

 * as setup by the bootloader to determine our window size.

 */

extern unsigned long ixp4xx_exp_bus_size;



#define	IXP4XX_EXP_BUS_BASE(region)\

		(IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))



#define IXP4XX_EXP_BUS_END(region)\

		(IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)



/* Those macros can be used to adjust timing and configure

 * other features for each region.

 */



#define IXP4XX_EXP_BUS_RECOVERY_T(x)	(((x) & 0x0f) << 16)

#define IXP4XX_EXP_BUS_HOLD_T(x)	(((x) & 0x03) << 20)

#define IXP4XX_EXP_BUS_STROBE_T(x)	(((x) & 0x0f) << 22)

#define IXP4XX_EXP_BUS_SETUP_T(x)	(((x) & 0x03) << 26)

#define IXP4XX_EXP_BUS_ADDR_T(x)	(((x) & 0x03) << 28)

#define IXP4XX_EXP_BUS_SIZE(x)		(((x) & 0x0f) << 10)

#define IXP4XX_EXP_BUS_CYCLES(x)	(((x) & 0x03) << 14)



#define IXP4XX_EXP_BUS_CS_EN		(1L << 31)

#define IXP4XX_EXP_BUS_BYTE_RD16	(1L << 6)

#define IXP4XX_EXP_BUS_HRDY_POL		(1L << 5)

#define IXP4XX_EXP_BUS_MUX_EN		(1L << 4)

#define IXP4XX_EXP_BUS_SPLT_EN		(1L << 3)

#define IXP4XX_EXP_BUS_WR_EN		(1L << 1)

#define IXP4XX_EXP_BUS_BYTE_EN		(1L << 0)



#define IXP4XX_EXP_BUS_CYCLES_INTEL	0x00

#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA	0x01

#define IXP4XX_EXP_BUS_CYCLES_HPI	0x02



#define IXP4XX_FLASH_WRITABLE	(0x2)

#define IXP4XX_FLASH_DEFAULT	(0xbcd23c40)

#define IXP4XX_FLASH_WRITE	(0xbcd23c42)



/*

 * Clock Speed Definitions.

 */

#define IXP4XX_PERIPHERAL_BUS_CLOCK 	(66) /* 66MHzi APB BUS   */ 

#define IXP4XX_UART_XTAL        	14745600



/*

 * Frequency of clock used for primary clocksource

 */

extern unsigned long ixp4xx_timer_freq;



/*

 * Functions used by platform-level setup code

 */

extern void ixp4xx_map_io(void);

extern void ixp4xx_init_early(void);

extern void ixp4xx_init_irq(void);

extern void ixp4xx_sys_init(void);

extern void ixp4xx_timer_init(void);

extern void ixp4xx_restart(enum reboot_mode, const char *);



#endif // __ASSEMBLY__