Commit 18b1746b authored by Aharon Landau's avatar Aharon Landau Committed by Jason Gunthorpe
Browse files

RDMA/mlx5: Remove implicit ODP cache entry 

Implicit ODP mkey doesn't have unique properties. It shares the same
properties as the order 18 cache entry. There is no need to devote a
special entry for that.

Link: https://lore.kernel.org/r/20230125222807.6921-3-michaelgur@nvidia.com


Signed-off-by: default avatarAharon Landau <aharonl@nvidia.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent a2a88b8e

drivers/infiniband/hw/mlx5/odp.c

+5 −15
Original line number Diff line number Diff line
@@ -405,6 +405,7 @@ static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev, 
static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr,

						unsigned long idx)

{

	int order = order_base_2(MLX5_IMR_MTT_ENTRIES);

	struct mlx5_ib_dev *dev = mr_to_mdev(imr);

	struct ib_umem_odp *odp;

	struct mlx5_ib_mr *mr;
@@ -417,7 +418,8 @@ static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr, 
	if (IS_ERR(odp))

		return ERR_CAST(odp);



	mr = mlx5_mr_cache_alloc(dev, &dev->cache.ent[MLX5_IMR_MTT_CACHE_ENTRY],

	BUILD_BUG_ON(order > MKEY_CACHE_LAST_STD_ENTRY);

	mr = mlx5_mr_cache_alloc(dev, &dev->cache.ent[order],

				 imr->access_flags);

	if (IS_ERR(mr)) {

		ib_umem_odp_release(odp);
@@ -1591,20 +1593,8 @@ void mlx5_odp_init_mkey_cache_entry(struct mlx5_cache_ent *ent) 
{

	if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))

		return;



	switch (ent->order - 2) {

	case MLX5_IMR_MTT_CACHE_ENTRY:

		ent->ndescs = MLX5_IMR_MTT_ENTRIES;

		ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;

		ent->limit = 0;

		break;



	case MLX5_IMR_KSM_CACHE_ENTRY:

	ent->ndescs = mlx5_imr_ksm_entries;

	ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;

		ent->limit = 0;

		break;

	}

}



static const struct ib_device_ops mlx5_ib_dev_odp_ops = {

include/linux/mlx5/driver.h

+0 −1
Original line number Diff line number Diff line
@@ -734,7 +734,6 @@ enum { 


enum {

	MKEY_CACHE_LAST_STD_ENTRY = 20,

	MLX5_IMR_MTT_CACHE_ENTRY,

	MLX5_IMR_KSM_CACHE_ENTRY,

	MAX_MKEY_CACHE_ENTRIES

};