Commit 18a8e864 authored by Li Yang's avatar Li Yang Committed by Jeff Garzik
Browse files

[PATCH] ucc_geth: changes to ucc_geth driver as a result of qe_lib changes and bugfixes 



changes due to qe_lib changes include:

o removed inclusion of platform header file
o removed platform_device code, replaced with of_device
o removed typedefs
o uint -> u32 conversions
o removed following defines:
  QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER,
  BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET
  because they hid sizeof/in_be32/out_be32 operations from the reader.
o removed irrelevant comments, added others to resemble removed BD_ defines
o const'd and uncasted all get_property() assignments

bugfixes, courtesy of Scott Wood, include:

- Read phy_address as a u32, not u8.
- Match on type == "network" as well as compatible == "ucc_geth", as
  device_is_compatible() will only compare up to the length of the
  test string, allowing "ucc_geth_phy" to match as well.
- fixes the MAC setting code in ucc_geth.c.  The old code was overwriting and dereferencing random stack contents.

Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 470ea7eb

drivers/net/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2288,7 +2288,7 @@ config UGETH_TX_ON_DEMOND 


config UGETH_HAS_GIGA

	bool

	depends on UCC_GETH && MPC836x

	depends on UCC_GETH && PPC_MPC836x



config MV643XX_ETH

	tristate "MV-643XX Ethernet support"

drivers/net/ucc_geth.c

+344 −289

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ucc_geth.h

+123 −125
Original line number Diff line number Diff line
@@ -36,24 +36,24 @@ 
#define ENET_INIT_PARAM_MAX_ENTRIES_RX  9

#define ENET_INIT_PARAM_MAX_ENTRIES_TX  8



typedef struct ucc_mii_mng {

struct ucc_mii_mng {

	u32 miimcfg;		/* MII management configuration reg */

	u32 miimcom;		/* MII management command reg */

	u32 miimadd;		/* MII management address reg */

	u32 miimcon;		/* MII management control reg */

	u32 miimstat;		/* MII management status reg */

	u32 miimind;		/* MII management indication reg */

} __attribute__ ((packed)) ucc_mii_mng_t;

} __attribute__ ((packed));



typedef struct ucc_geth {

	ucc_fast_t uccf;

struct ucc_geth {

	struct ucc_fast uccf;



	u32 maccfg1;		/* mac configuration reg. 1 */

	u32 maccfg2;		/* mac configuration reg. 2 */

	u32 ipgifg;		/* interframe gap reg.  */

	u32 hafdup;		/* half-duplex reg.  */

	u8 res1[0x10];

	ucc_mii_mng_t miimng;	/* MII management structure */

	struct ucc_mii_mng miimng;	/* MII management structure */

	u32 ifctl;		/* interface control reg */

	u32 ifstat;		/* interface statux reg */

	u32 macstnaddr1;	/* mac station address part 1 reg */
@@ -111,7 +111,7 @@ typedef struct ucc_geth { 
	u32 scar;		/* Statistics carry register */

	u32 scam;		/* Statistics caryy mask register */

	u8 res5[0x200 - 0x1c4];

} __attribute__ ((packed)) ucc_geth_t;

} __attribute__ ((packed));



/* UCC GETH TEMODR Register */

#define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100	/* enable Tx statistics
@@ -508,39 +508,39 @@ typedef struct ucc_geth { 
/* UCC GETH UDSR (Data Synchronization Register) */

#define UDSR_MAGIC                              0x067E



typedef struct ucc_geth_thread_data_tx {

struct ucc_geth_thread_data_tx {

	u8 res0[104];

} __attribute__ ((packed)) ucc_geth_thread_data_tx_t;

} __attribute__ ((packed));



typedef struct ucc_geth_thread_data_rx {

struct ucc_geth_thread_data_rx {

	u8 res0[40];

} __attribute__ ((packed)) ucc_geth_thread_data_rx_t;

} __attribute__ ((packed));



/* Send Queue Queue-Descriptor */

typedef struct ucc_geth_send_queue_qd {

struct ucc_geth_send_queue_qd {

	u32 bd_ring_base;	/* pointer to BD ring base address */

	u8 res0[0x8];

	u32 last_bd_completed_address;/* initialize to last entry in BD ring */

	u8 res1[0x30];

} __attribute__ ((packed)) ucc_geth_send_queue_qd_t;

} __attribute__ ((packed));



typedef struct ucc_geth_send_queue_mem_region {

	ucc_geth_send_queue_qd_t sqqd[NUM_TX_QUEUES];

} __attribute__ ((packed)) ucc_geth_send_queue_mem_region_t;

struct ucc_geth_send_queue_mem_region {

	struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];

} __attribute__ ((packed));



typedef struct ucc_geth_thread_tx_pram {

struct ucc_geth_thread_tx_pram {

	u8 res0[64];

} __attribute__ ((packed)) ucc_geth_thread_tx_pram_t;

} __attribute__ ((packed));



typedef struct ucc_geth_thread_rx_pram {

struct ucc_geth_thread_rx_pram {

	u8 res0[128];

} __attribute__ ((packed)) ucc_geth_thread_rx_pram_t;

} __attribute__ ((packed));



#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64

#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64

#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96



typedef struct ucc_geth_scheduler {

struct ucc_geth_scheduler {

	u16 cpucount0;		/* CPU packet counter */

	u16 cpucount1;		/* CPU packet counter */

	u16 cecount0;		/* QE packet counter */
@@ -574,9 +574,9 @@ typedef struct ucc_geth_scheduler { 
				      /**< weight factor for queues   */

	u32 minw;		/* temporary variable handled by QE */

	u8 res1[0x70 - 0x64];

} __attribute__ ((packed)) ucc_geth_scheduler_t;

} __attribute__ ((packed));



typedef struct ucc_geth_tx_firmware_statistics_pram {

struct ucc_geth_tx_firmware_statistics_pram {

	u32 sicoltx;		/* single collision */

	u32 mulcoltx;		/* multiple collision */

	u32 latecoltxfr;	/* late collision */
@@ -596,9 +596,9 @@ typedef struct ucc_geth_tx_firmware_statistics_pram { 
				   and 1518 octets */

	u32 txpktsjumbo;	/* total packets (including bad) between 1024

				   and MAXLength octets */

} __attribute__ ((packed)) ucc_geth_tx_firmware_statistics_pram_t;

} __attribute__ ((packed));



typedef struct ucc_geth_rx_firmware_statistics_pram {

struct ucc_geth_rx_firmware_statistics_pram {

	u32 frrxfcser;		/* frames with crc error */

	u32 fraligner;		/* frames with alignment error */

	u32 inrangelenrxer;	/* in range length error */
@@ -630,33 +630,33 @@ typedef struct ucc_geth_rx_firmware_statistics_pram { 
				   replaced */

	u32 insertvlan;		/* total frames that had their VLAN tag

				   inserted */

} __attribute__ ((packed)) ucc_geth_rx_firmware_statistics_pram_t;

} __attribute__ ((packed));



typedef struct ucc_geth_rx_interrupt_coalescing_entry {

struct ucc_geth_rx_interrupt_coalescing_entry {

	u32 interruptcoalescingmaxvalue;	/* interrupt coalescing max

						   value */

	u32 interruptcoalescingcounter;	/* interrupt coalescing counter,

					   initialize to

					   interruptcoalescingmaxvalue */

} __attribute__ ((packed)) ucc_geth_rx_interrupt_coalescing_entry_t;

} __attribute__ ((packed));



typedef struct ucc_geth_rx_interrupt_coalescing_table {

	ucc_geth_rx_interrupt_coalescing_entry_t coalescingentry[NUM_RX_QUEUES];

struct ucc_geth_rx_interrupt_coalescing_table {

	struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];

				       /**< interrupt coalescing entry */

} __attribute__ ((packed)) ucc_geth_rx_interrupt_coalescing_table_t;

} __attribute__ ((packed));



typedef struct ucc_geth_rx_prefetched_bds {

	qe_bd_t bd[NUM_BDS_IN_PREFETCHED_BDS];	/* prefetched bd */

} __attribute__ ((packed)) ucc_geth_rx_prefetched_bds_t;

struct ucc_geth_rx_prefetched_bds {

	struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];	/* prefetched bd */

} __attribute__ ((packed));



typedef struct ucc_geth_rx_bd_queues_entry {

struct ucc_geth_rx_bd_queues_entry {

	u32 bdbaseptr;		/* BD base pointer */

	u32 bdptr;		/* BD pointer */

	u32 externalbdbaseptr;	/* external BD base pointer */

	u32 externalbdptr;	/* external BD pointer */

} __attribute__ ((packed)) ucc_geth_rx_bd_queues_entry_t;

} __attribute__ ((packed));



typedef struct ucc_geth_tx_global_pram {

struct ucc_geth_tx_global_pram {

	u16 temoder;

	u8 res0[0x38 - 0x02];

	u32 sqptr;		/* a base pointer to send queue memory region */
@@ -670,15 +670,15 @@ typedef struct ucc_geth_tx_global_pram { 
	u32 tqptr;		/* a base pointer to the Tx Queues Memory

				   Region */

	u8 res2[0x80 - 0x74];

} __attribute__ ((packed)) ucc_geth_tx_global_pram_t;

} __attribute__ ((packed));



/* structure representing Extended Filtering Global Parameters in PRAM */

typedef struct ucc_geth_exf_global_pram {

struct ucc_geth_exf_global_pram {

	u32 l2pcdptr;		/* individual address filter, high */

	u8 res0[0x10 - 0x04];

} __attribute__ ((packed)) ucc_geth_exf_global_pram_t;

} __attribute__ ((packed));



typedef struct ucc_geth_rx_global_pram {

struct ucc_geth_rx_global_pram {

	u32 remoder;		/* ethernet mode reg. */

	u32 rqptr;		/* base pointer to the Rx Queues Memory Region*/

	u32 res0[0x1];
@@ -710,12 +710,12 @@ typedef struct ucc_geth_rx_global_pram { 
	u32 exfGlobalParam;	/* base address for extended filtering global

				   parameters */

	u8 res6[0x100 - 0xC4];	/* Initialize to zero */

} __attribute__ ((packed)) ucc_geth_rx_global_pram_t;

} __attribute__ ((packed));



#define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01



/* structure representing InitEnet command */

typedef struct ucc_geth_init_pram {

struct ucc_geth_init_pram {

	u8 resinit1;

	u8 resinit2;

	u8 resinit3;
@@ -729,7 +729,7 @@ typedef struct ucc_geth_init_pram { 
	u32 txglobal;		/* tx global */

	u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];	/* tx threads */

	u8 res3[0x1];

} __attribute__ ((packed)) ucc_geth_init_pram_t;

} __attribute__ ((packed));



#define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)

#define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
@@ -746,27 +746,27 @@ typedef struct ucc_geth_init_pram { 
#define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400



/* structure representing 82xx Address Filtering Enet Address in PRAM */

typedef struct ucc_geth_82xx_enet_address {

struct ucc_geth_82xx_enet_address {

	u8 res1[0x2];

	u16 h;			/* address (MSB) */

	u16 m;			/* address */

	u16 l;			/* address (LSB) */

} __attribute__ ((packed)) ucc_geth_82xx_enet_address_t;

} __attribute__ ((packed));



/* structure representing 82xx Address Filtering PRAM */

typedef struct ucc_geth_82xx_address_filtering_pram {

struct ucc_geth_82xx_address_filtering_pram {

	u32 iaddr_h;		/* individual address filter, high */

	u32 iaddr_l;		/* individual address filter, low */

	u32 gaddr_h;		/* group address filter, high */

	u32 gaddr_l;		/* group address filter, low */

	ucc_geth_82xx_enet_address_t taddr;

	ucc_geth_82xx_enet_address_t paddr[NUM_OF_PADDRS];

	struct ucc_geth_82xx_enet_address taddr;

	struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS];

	u8 res0[0x40 - 0x38];

} __attribute__ ((packed)) ucc_geth_82xx_address_filtering_pram_t;

} __attribute__ ((packed));



/* GETH Tx firmware statistics structure, used when calling

   UCC_GETH_GetStatistics. */

typedef struct ucc_geth_tx_firmware_statistics {

struct ucc_geth_tx_firmware_statistics {

	u32 sicoltx;		/* single collision */

	u32 mulcoltx;		/* multiple collision */

	u32 latecoltxfr;	/* late collision */
@@ -786,11 +786,11 @@ typedef struct ucc_geth_tx_firmware_statistics { 
				   and 1518 octets */

	u32 txpktsjumbo;	/* total packets (including bad) between 1024

				   and MAXLength octets */

} __attribute__ ((packed)) ucc_geth_tx_firmware_statistics_t;

} __attribute__ ((packed));



/* GETH Rx firmware statistics structure, used when calling

   UCC_GETH_GetStatistics. */

typedef struct ucc_geth_rx_firmware_statistics {

struct ucc_geth_rx_firmware_statistics {

	u32 frrxfcser;		/* frames with crc error */

	u32 fraligner;		/* frames with alignment error */

	u32 inrangelenrxer;	/* in range length error */
@@ -822,11 +822,11 @@ typedef struct ucc_geth_rx_firmware_statistics { 
				   replaced */

	u32 insertvlan;		/* total frames that had their VLAN tag

				   inserted */

} __attribute__ ((packed)) ucc_geth_rx_firmware_statistics_t;

} __attribute__ ((packed));



/* GETH hardware statistics structure, used when calling

   UCC_GETH_GetStatistics. */

typedef struct ucc_geth_hardware_statistics {

struct ucc_geth_hardware_statistics {

	u32 tx64;		/* Total number of frames (including bad

				   frames) transmitted that were exactly of the

				   minimal length (64 for un tagged, 68 for
@@ -871,7 +871,7 @@ typedef struct ucc_geth_hardware_statistics { 
	u32 rbca;		/* Total number of frames received succesfully

				   that had destination address equal to the

				   broadcast address */

} __attribute__ ((packed)) ucc_geth_hardware_statistics_t;

} __attribute__ ((packed));



/* UCC GETH Tx errors returned via TxConf callback */

#define TX_ERRORS_DEF      0x0200
@@ -1013,21 +1013,21 @@ typedef struct ucc_geth_hardware_statistics { 
				(MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112)



/* Ethernet speed */

typedef enum enet_speed {

enum enet_speed {

	ENET_SPEED_10BT,	/* 10 Base T */

	ENET_SPEED_100BT,	/* 100 Base T */

	ENET_SPEED_1000BT	/* 1000 Base T */

} enet_speed_e;

};



/* Ethernet Address Type. */

typedef enum enet_addr_type {

enum enet_addr_type {

	ENET_ADDR_TYPE_INDIVIDUAL,

	ENET_ADDR_TYPE_GROUP,

	ENET_ADDR_TYPE_BROADCAST

} enet_addr_type_e;

};



/* TBI / MII Set Register */

typedef enum enet_tbi_mii_reg {

enum enet_tbi_mii_reg {

	ENET_TBI_MII_CR = 0x00,	/* Control (CR ) */

	ENET_TBI_MII_SR = 0x01,	/* Status (SR ) */

	ENET_TBI_MII_ANA = 0x04,	/* AN advertisement (ANA ) */
@@ -1040,10 +1040,10 @@ typedef enum enet_tbi_mii_reg { 
	ENET_TBI_MII_EXST = 0x0F,	/* Extended status (EXST ) */

	ENET_TBI_MII_JD = 0x10,	/* Jitter diagnostics (JD ) */

	ENET_TBI_MII_TBICON = 0x11	/* TBI control (TBICON ) */

} enet_tbi_mii_reg_e;

};



/* UCC GETH 82xx Ethernet Address Recognition Location */

typedef enum ucc_geth_enet_address_recognition_location {

enum ucc_geth_enet_address_recognition_location {

	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station

								      address */

	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST,	/* additional
@@ -1065,10 +1065,10 @@ typedef enum ucc_geth_enet_address_recognition_location { 
	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,	/* group hash */

	UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual

								      hash */

} ucc_geth_enet_address_recognition_location_e;

};



/* UCC GETH vlan operation tagged */

typedef enum ucc_geth_vlan_operation_tagged {

enum ucc_geth_vlan_operation_tagged {

	UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,	/* Tagged - nop */

	UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG

		= 0x1,	/* Tagged - replace vid portion of q tag */
@@ -1076,18 +1076,18 @@ typedef enum ucc_geth_vlan_operation_tagged { 
		= 0x2,	/* Tagged - if vid0 replace vid with default value  */

	UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME

		= 0x3	/* Tagged - extract q tag from frame */

} ucc_geth_vlan_operation_tagged_e;

};



/* UCC GETH vlan operation non-tagged */

typedef enum ucc_geth_vlan_operation_non_tagged {

enum ucc_geth_vlan_operation_non_tagged {

	UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,	/* Non tagged - nop */

	UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1	/* Non tagged -

								   q tag insert

								 */

} ucc_geth_vlan_operation_non_tagged_e;

};



/* UCC GETH Rx Quality of Service Mode */

typedef enum ucc_geth_qos_mode {

enum ucc_geth_qos_mode {

	UCC_GETH_QOS_MODE_DEFAULT = 0x0,	/* default queue */

	UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,	/* queue

								   determined
@@ -1097,11 +1097,11 @@ typedef enum ucc_geth_qos_mode { 
								   determined

								   by L3

								   criteria */

} ucc_geth_qos_mode_e;

};



/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together

   for combined functionality */

typedef enum ucc_geth_statistics_gathering_mode {

enum ucc_geth_statistics_gathering_mode {

	UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,	/* No

								   statistics

								   gathering */
@@ -1122,10 +1122,10 @@ typedef enum ucc_geth_statistics_gathering_mode { 
								      statistics

								      gathering

								    */

} ucc_geth_statistics_gathering_mode_e;

};



/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */

typedef enum ucc_geth_maccfg2_pad_and_crc_mode {

enum ucc_geth_maccfg2_pad_and_crc_mode {

	UCC_GETH_PAD_AND_CRC_MODE_NONE

		= MACCFG2_PAD_AND_CRC_MODE_NONE,	/* Neither Padding

							   short frames
@@ -1135,61 +1135,59 @@ typedef enum ucc_geth_maccfg2_pad_and_crc_mode { 
							   CRC only */

	UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =

	    MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC

} ucc_geth_maccfg2_pad_and_crc_mode_e;

};



/* UCC GETH upsmr Flow Control Mode */

typedef enum ucc_geth_flow_control_mode {

enum ucc_geth_flow_control_mode {

	UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,	/* No automatic

								   flow control

								 */

	UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY

		= 0x00004000	/* Send pause frame when RxFIFO reaches its

				   emergency threshold */

} ucc_geth_flow_control_mode_e;

};



/* UCC GETH number of threads */

typedef enum ucc_geth_num_of_threads {

enum ucc_geth_num_of_threads {

	UCC_GETH_NUM_OF_THREADS_1 = 0x1,	/* 1 */

	UCC_GETH_NUM_OF_THREADS_2 = 0x2,	/* 2 */

	UCC_GETH_NUM_OF_THREADS_4 = 0x0,	/* 4 */

	UCC_GETH_NUM_OF_THREADS_6 = 0x3,	/* 6 */

	UCC_GETH_NUM_OF_THREADS_8 = 0x4	/* 8 */

} ucc_geth_num_of_threads_e;

};



/* UCC GETH number of station addresses */

typedef enum ucc_geth_num_of_station_addresses {

enum ucc_geth_num_of_station_addresses {

	UCC_GETH_NUM_OF_STATION_ADDRESSES_1,	/* 1 */

	UCC_GETH_NUM_OF_STATION_ADDRESSES_5	/* 5 */

} ucc_geth_num_of_station_addresses_e;



typedef u8 enet_addr_t[ENET_NUM_OCTETS_PER_ADDRESS];

};



/* UCC GETH 82xx Ethernet Address Container */

typedef struct enet_addr_container {

	enet_addr_t address;	/* ethernet address */

	ucc_geth_enet_address_recognition_location_e location;	/* location in

struct enet_addr_container {

	u8 address[ENET_NUM_OCTETS_PER_ADDRESS];	/* ethernet address */

	enum ucc_geth_enet_address_recognition_location location;	/* location in

								   82xx address

								   recognition

								   hardware */

	struct list_head node;

} enet_addr_container_t;

};



#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, enet_addr_container_t, node)

#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)



/* UCC GETH Termination Action Descriptor (TAD) structure. */

typedef struct ucc_geth_tad_params {

struct ucc_geth_tad_params {

	int rx_non_dynamic_extended_features_mode;

	int reject_frame;

	ucc_geth_vlan_operation_tagged_e vtag_op;

	ucc_geth_vlan_operation_non_tagged_e vnontag_op;

	ucc_geth_qos_mode_e rqos;

	enum ucc_geth_vlan_operation_tagged vtag_op;

	enum ucc_geth_vlan_operation_non_tagged vnontag_op;

	enum ucc_geth_qos_mode rqos;

	u8 vpri;

	u16 vid;

} ucc_geth_tad_params_t;

};



/* GETH protocol initialization structure */

typedef struct ucc_geth_info {

	ucc_fast_info_t uf_info;

struct ucc_geth_info {

	struct ucc_fast_info uf_info;

	u8 numQueuesTx;

	u8 numQueuesRx;

	int ipCheckSumCheck;
@@ -1251,51 +1249,51 @@ typedef struct ucc_geth_info { 
	u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];

	u16 bdRingLenTx[NUM_TX_QUEUES];

	u16 bdRingLenRx[NUM_RX_QUEUES];

	enet_interface_e enet_interface;

	ucc_geth_num_of_station_addresses_e numStationAddresses;

	 qe_fltr_largest_external_tbl_lookup_key_size_e

	enum enet_interface enet_interface;

	enum ucc_geth_num_of_station_addresses numStationAddresses;

	enum qe_fltr_largest_external_tbl_lookup_key_size

	    largestexternallookupkeysize;

	ucc_geth_statistics_gathering_mode_e statisticsMode;

	ucc_geth_vlan_operation_tagged_e vlanOperationTagged;

	ucc_geth_vlan_operation_non_tagged_e vlanOperationNonTagged;

	ucc_geth_qos_mode_e rxQoSMode;

	ucc_geth_flow_control_mode_e aufc;

	ucc_geth_maccfg2_pad_and_crc_mode_e padAndCrc;

	ucc_geth_num_of_threads_e numThreadsTx;

	ucc_geth_num_of_threads_e numThreadsRx;

	qe_risc_allocation_e riscTx;

	qe_risc_allocation_e riscRx;

} ucc_geth_info_t;

	enum ucc_geth_statistics_gathering_mode statisticsMode;

	enum ucc_geth_vlan_operation_tagged vlanOperationTagged;

	enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;

	enum ucc_geth_qos_mode rxQoSMode;

	enum ucc_geth_flow_control_mode aufc;

	enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;

	enum ucc_geth_num_of_threads numThreadsTx;

	enum ucc_geth_num_of_threads numThreadsRx;

	enum qe_risc_allocation riscTx;

	enum qe_risc_allocation riscRx;

};



/* structure representing UCC GETH */

typedef struct ucc_geth_private {

	ucc_geth_info_t *ug_info;

	ucc_fast_private_t *uccf;

struct ucc_geth_private {

	struct ucc_geth_info *ug_info;

	struct ucc_fast_private *uccf;

	struct net_device *dev;

	struct net_device_stats stats;	/* linux network statistics */

	ucc_geth_t *ug_regs;

	ucc_geth_init_pram_t *p_init_enet_param_shadow;

	ucc_geth_exf_global_pram_t *p_exf_glbl_param;

	struct ucc_geth *ug_regs;

	struct ucc_geth_init_pram *p_init_enet_param_shadow;

	struct ucc_geth_exf_global_pram *p_exf_glbl_param;

	u32 exf_glbl_param_offset;

	ucc_geth_rx_global_pram_t *p_rx_glbl_pram;

	struct ucc_geth_rx_global_pram *p_rx_glbl_pram;

	u32 rx_glbl_pram_offset;

	ucc_geth_tx_global_pram_t *p_tx_glbl_pram;

	struct ucc_geth_tx_global_pram *p_tx_glbl_pram;

	u32 tx_glbl_pram_offset;

	ucc_geth_send_queue_mem_region_t *p_send_q_mem_reg;

	struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg;

	u32 send_q_mem_reg_offset;

	ucc_geth_thread_data_tx_t *p_thread_data_tx;

	struct ucc_geth_thread_data_tx *p_thread_data_tx;

	u32 thread_dat_tx_offset;

	ucc_geth_thread_data_rx_t *p_thread_data_rx;

	struct ucc_geth_thread_data_rx *p_thread_data_rx;

	u32 thread_dat_rx_offset;

	ucc_geth_scheduler_t *p_scheduler;

	struct ucc_geth_scheduler *p_scheduler;

	u32 scheduler_offset;

	ucc_geth_tx_firmware_statistics_pram_t *p_tx_fw_statistics_pram;

	struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;

	u32 tx_fw_statistics_pram_offset;

	ucc_geth_rx_firmware_statistics_pram_t *p_rx_fw_statistics_pram;

	struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;

	u32 rx_fw_statistics_pram_offset;

	ucc_geth_rx_interrupt_coalescing_table_t *p_rx_irq_coalescing_tbl;

	struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl;

	u32 rx_irq_coalescing_tbl_offset;

	ucc_geth_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;

	struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl;

	u32 rx_bd_qs_tbl_offset;

	u8 *p_tx_bd_ring[NUM_TX_QUEUES];

	u32 tx_bd_ring_offset[NUM_TX_QUEUES];
@@ -1308,7 +1306,7 @@ typedef struct ucc_geth_private { 
	u16 cpucount[NUM_TX_QUEUES];

	volatile u16 *p_cpucount[NUM_TX_QUEUES];

	int indAddrRegUsed[NUM_OF_PADDRS];

	enet_addr_t paddr[NUM_OF_PADDRS];

	u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS];	/* ethernet address */

	u8 numGroupAddrInHash;

	u8 numIndAddrInHash;

	u8 numIndAddrInReg;
@@ -1334,6 +1332,6 @@ typedef struct ucc_geth_private { 
	int oldspeed;

	int oldduplex;

	int oldlink;

} ucc_geth_private_t;

};



#endif				/* __UCC_GETH_H__ */

drivers/net/ucc_geth_phy.c

+6 −20
Original line number Diff line number Diff line
@@ -42,7 +42,6 @@ 


#include "ucc_geth.h"

#include "ucc_geth_phy.h"

#include <platforms/83xx/mpc8360e_pb.h>



#define ugphy_printk(level, format, arg...)  \

        printk(level format "\n", ## arg)
@@ -72,16 +71,14 @@ static int genmii_read_status(struct ugeth_mii_info *mii_info); 
u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum);

void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val);



static u8 *bcsr_regs = NULL;



/* Write value to the PHY for this device to the register at regnum, */

/* waiting until the write is done before it returns.  All PHY */

/* configuration has to be done through the TSEC1 MIIM regs */

void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)

{

	ucc_geth_private_t *ugeth = netdev_priv(dev);

	ucc_mii_mng_t *mii_regs;

	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;

	struct ucc_geth_private *ugeth = netdev_priv(dev);

	struct ucc_mii_mng *mii_regs;

	enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;

	u32 tmp_reg;



	ugphy_vdbg("%s: IN", __FUNCTION__);
@@ -116,9 +113,9 @@ void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value) 
/* configuration has to be done through the TSEC1 MIIM regs */

int read_phy_reg(struct net_device *dev, int mii_id, int regnum)

{

	ucc_geth_private_t *ugeth = netdev_priv(dev);

	ucc_mii_mng_t *mii_regs;

	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;

	struct ucc_geth_private *ugeth = netdev_priv(dev);

	struct ucc_mii_mng *mii_regs;

	enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;

	u32 tmp_reg;

	u16 value;
@@ -634,11 +631,6 @@ static void dm9161_close(struct ugeth_mii_info *mii_info) 


static int dm9161_ack_interrupt(struct ugeth_mii_info *mii_info)

{

/* FIXME: This lines are for BUG fixing in the mpc8325.

Remove this from here when it's fixed */

	if (bcsr_regs == NULL)

		bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);

	bcsr_regs[14] |= 0x40;

	ugphy_vdbg("%s: IN", __FUNCTION__);



	/* Clear the interrupts by reading the reg */
@@ -650,12 +642,6 @@ Remove this from here when it's fixed */ 


static int dm9161_config_intr(struct ugeth_mii_info *mii_info)

{

/* FIXME: This lines are for BUG fixing in the mpc8325.

Remove this from here when it's fixed */

	if (bcsr_regs == NULL) {

		bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);

		bcsr_regs[14] &= ~0x40;

	}

	ugphy_vdbg("%s: IN", __FUNCTION__);



	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)

drivers/net/ucc_geth_phy.h

+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ struct ugeth_mii_info { 
	/* And management functions */

	struct phy_info *phyinfo;



	ucc_mii_mng_t *mii_regs;

	struct ucc_mii_mng *mii_regs;



	/* forced speed & duplex (no autoneg)

	 * partner speed & duplex & pause (autoneg)