Commit 186ad90a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom: qmp-combo: reuse register layouts for even more registers 



Instead of passing additional registers to qmp_combo_configure_dp_swing(),
reuse qphy_reg_layout and add those registers to register layout maps.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-4-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 8447fa7f

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+71 −33
Original line number Diff line number Diff line
@@ -113,6 +113,10 @@ enum qphy_reg_layout { 


	QPHY_DP_PHY_STATUS,



	QPHY_TX_TX_POL_INV,

	QPHY_TX_TX_DRV_LVL,

	QPHY_TX_TX_EMP_POST1_LVL,



	/* Keep last to ensure regs_layout arrays are properly initialized */

	QPHY_LAYOUT_SIZE

};
@@ -130,6 +134,10 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_CMN_STATUS]		= QSERDES_V3_COM_CMN_STATUS,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V3_DP_PHY_STATUS,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V3_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V3_TX_TX_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]	= QSERDES_V3_TX_TX_EMP_POST1_LVL,

};



static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -147,6 +155,31 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_CMN_STATUS]		= QSERDES_V4_COM_CMN_STATUS,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V4_DP_PHY_STATUS,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V4_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V4_TX_TX_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]	= QSERDES_V4_TX_TX_EMP_POST1_LVL,

};



static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V5_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V5_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]		= QPHY_V5_PCS_PCS_STATUS1,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_POWER_DOWN_CONTROL,



	/* In PCS_USB */

	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,

	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,



	[QPHY_COM_RESETSM_CNTRL]	= QSERDES_V5_COM_RESETSM_CNTRL,

	[QPHY_COM_C_READY_STATUS]	= QSERDES_V5_COM_C_READY_STATUS,

	[QPHY_COM_CMN_STATUS]		= QSERDES_V5_COM_CMN_STATUS,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V5_DP_PHY_STATUS,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V5_5NM_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V5_5NM_TX_TX_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]	= QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,

};



static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -164,6 +197,10 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_CMN_STATUS]		= QSERDES_V6_COM_CMN_STATUS,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V6_DP_PHY_STATUS,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V6_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V6_TX_TX_DRV_LVL,

	[QPHY_TX_TX_EMP_POST1_LVL]	= QSERDES_V6_TX_TX_EMP_POST1_LVL,

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -1648,7 +1685,7 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 
	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qmp_v45_usb3phy_regs_layout,

	.regs			= qmp_v5_5nm_usb3phy_regs_layout,

};



static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
@@ -1942,8 +1979,7 @@ static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 
	       qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);

}



static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,

		unsigned int drv_lvl_reg, unsigned int emp_post_reg)

static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)

{

	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -1972,10 +2008,10 @@ static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp, 
	voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;

	pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;



	writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg);

	writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg);

	writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg);

	writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg);

	writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);

	writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);



	return 0;

}
@@ -1985,8 +2021,7 @@ static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 
	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	u32 bias_en, drvr_en;



	if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL,

				QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)

	if (qmp_combo_configure_dp_swing(qmp) < 0)

		return;



	if (dp_opts->lanes == 1) {
@@ -2174,15 +2209,16 @@ static void qmp_v6_dp_aux_init(struct qmp_combo *qmp) 


static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)

{

	const struct qmp_phy_cfg *cfg = qmp->cfg;



	/* Program default values before writing proper values */

	writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);



	writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);

	writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);



	qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL,

			QSERDES_V4_TX_TX_EMP_POST1_LVL);

	qmp_combo_configure_dp_swing(qmp);

}



static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
@@ -2326,14 +2362,16 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 
			10000))

		return -ETIMEDOUT;



	writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);

	writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);



	writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);



	writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);

	writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);



	return 0;



	return 0;

}
@@ -2384,14 +2422,14 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) 
			10000))

		return -ETIMEDOUT;



	writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);

	writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);



	writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);



	writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);

	writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);



	return 0;

}
@@ -2442,14 +2480,14 @@ static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp) 
			       10000))

		return -ETIMEDOUT;



	writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);

	writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);

	writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);



	writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);

	writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);

	writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);



	writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);

	writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);

	writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);



	return 0;

}

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h

+3 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 
#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_



#define QSERDES_V6_TX_CLKBUF_ENABLE				0x08

#define QSERDES_V6_TX_TX_EMP_POST1_LVL				0x0c

#define QSERDES_V6_TX_TX_DRV_LVL				0x14

#define QSERDES_V6_TX_RESET_TSYNC_EN				0x1c

#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN			0x20

#define QSERDES_V6_TX_TX_BAND					0x24
@@ -15,6 +17,7 @@ 
#define QSERDES_V6_TX_RES_CODE_LANE_RX				0x38

#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX			0x3c

#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX			0x40

#define QSERDES_V6_TX_TX_POL_INV				0x5c

#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN		0x60

#define QSERDES_V6_TX_BIST_PATTERN7				0x7c

#define QSERDES_V6_TX_LANE_MODE_1				0x84

drivers/phy/qualcomm/phy-qcom-qmp.h

+2 −0
Original line number Diff line number Diff line
@@ -134,6 +134,8 @@ 
#define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10

#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14



#define QSERDES_V5_DP_PHY_STATUS			0x0dc



/* Only for QMP V6 PHY - DP PHY registers */

#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS		0x0e0

#define QSERDES_V6_DP_PHY_STATUS			0x0e4