Commit 184f37e5 authored by Jagan Teki's avatar Jagan Teki Committed by Inki Dae
Browse files

drm: exynos: dsi: Add input_bus_flags 



LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting
the i.MX8M Mini/Nano DSI host to add additional Data Enable signal
active low (DE_LOW). This makes the valid data transfer on each
horizontal line.

So, add additional bus flags DE_LOW setting via input_bus_flags
for i.MX8M Mini/Nano platforms.

Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
Suggested-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 88576e23

drivers/gpu/drm/exynos/exynos_drm_dsi.c

+8 −0
Original line number Diff line number Diff line
@@ -1736,6 +1736,10 @@ static const struct component_ops exynos_dsi_component_ops = { 
	.unbind	= exynos_dsi_unbind,

};



static const struct drm_bridge_timings dsim_bridge_timings_de_low = {

	.input_bus_flags = DRM_BUS_FLAG_DE_LOW,

};



static int exynos_dsi_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -1822,6 +1826,10 @@ static int exynos_dsi_probe(struct platform_device *pdev) 
	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;

	dsi->bridge.pre_enable_prev_first = true;



	/* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */

	if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)

		dsi->bridge.timings = &dsim_bridge_timings_de_low;



	ret = component_add(dev, &exynos_dsi_component_ops);

	if (ret)

		goto err_disable_runtime;