Commit 183ca111 authored by Felipe Balbi's avatar Felipe Balbi
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usb: dwc3: core: define bit 10 of GCTL register 



This bit is necessary for implemeting workaround
for known issue with some revisions of this core.

Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent f3af3651

drivers/usb/dwc3/core.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ 
#define DWC3_GCTL_PRTCAP_OTG	3



#define DWC3_GCTL_CORESOFTRESET		(1 << 11)

#define DWC3_GCTL_SOFITPSYNC		(1 << 10)

#define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)

#define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)

#define DWC3_GCTL_DISSCRAMBLE		(1 << 3)