Loading Documentation/devicetree/bindings/sound/fsl-sai.txt +7 −2 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ codec/DSP interfaces. Required properties: - compatible : Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". - compatible : Compatible list, contains "fsl,vf610-sai", "fsl,imx6sx-sai" or "fsl,imx6ul-sai" - reg : Offset and length of the register set for the device. Loading Loading @@ -48,6 +48,11 @@ Required properties: receive data by following their own bit clocks and frame sync clocks separately. Optional properties (for mx6ul): - fsl,sai-mclk-direction-output: This is a boolean property. If present, indicates that SAI will output the SAI MCLK clock. Note: - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the default synchronous mode (sync Rx with Tx) will be used, which means both Loading MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -4661,6 +4661,7 @@ FREESCALE SOC SOUND DRIVERS M: Timur Tabi <timur@tabi.org> M: Nicolin Chen <nicoleotsuka@gmail.com> M: Xiubo Li <Xiubo.Lee@gmail.com> R: Fabio Estevam <fabio.estevam@nxp.com> L: alsa-devel@alsa-project.org (moderated for non-subscribers) L: linuxppc-dev@lists.ozlabs.org S: Maintained Loading include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +6 −0 Original line number Diff line number Diff line Loading @@ -447,5 +447,11 @@ #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) #define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17) #define IMX6UL_GPR1_SAI1_MCLK_DIR (0x1 << 19) #define IMX6UL_GPR1_SAI2_MCLK_DIR (0x1 << 20) #define IMX6UL_GPR1_SAI3_MCLK_DIR (0x1 << 21) #define IMX6UL_GPR1_SAI_MCLK_MASK (0x7 << 19) #define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \ IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR) #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ include/sound/soc.h +3 −0 Original line number Diff line number Diff line Loading @@ -1683,6 +1683,9 @@ void snd_soc_remove_dai_link(struct snd_soc_card *card, int snd_soc_register_dai(struct snd_soc_component *component, struct snd_soc_dai_driver *dai_drv); struct snd_soc_dai *snd_soc_find_dai( const struct snd_soc_dai_link_component *dlc); #include <sound/soc-dai.h> #ifdef CONFIG_DEBUG_FS Loading sound/soc/codecs/es8328.c +149 −45 Original line number Diff line number Diff line Loading @@ -26,18 +26,30 @@ #include <sound/tlv.h> #include "es8328.h" #define ES8328_SYSCLK_RATE_1X 11289600 #define ES8328_SYSCLK_RATE_2X 22579200 static const unsigned int rates_12288[] = { 8000, 12000, 16000, 24000, 32000, 48000, 96000, }; /* Run the codec at 22.5792 or 11.2896 MHz to support these rates */ static struct { int rate; u8 ratio; } mclk_ratios[] = { { 8000, 9 }, {11025, 7 }, {22050, 4 }, {44100, 2 }, static const int ratios_12288[] = { 10, 7, 6, 4, 3, 2, 0, }; static const struct snd_pcm_hw_constraint_list constraints_12288 = { .count = ARRAY_SIZE(rates_12288), .list = rates_12288, }; static const unsigned int rates_11289[] = { 8018, 11025, 22050, 44100, 88200, }; static const int ratios_11289[] = { 9, 7, 4, 2, 0, }; static const struct snd_pcm_hw_constraint_list constraints_11289 = { .count = ARRAY_SIZE(rates_11289), .list = rates_11289, }; /* regulator supplies for sgtl5000, VDDD is an optional external supply */ Loading @@ -57,16 +69,28 @@ static const char * const supply_names[ES8328_SUPPLY_NUM] = { "HPVDD", }; #define ES8328_RATES (SNDRV_PCM_RATE_44100 | \ #define ES8328_RATES (SNDRV_PCM_RATE_96000 | \ SNDRV_PCM_RATE_48000 | \ SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_32000 | \ SNDRV_PCM_RATE_22050 | \ SNDRV_PCM_RATE_11025) #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) SNDRV_PCM_RATE_16000 | \ SNDRV_PCM_RATE_11025 | \ SNDRV_PCM_RATE_8000) #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S18_3LE | \ SNDRV_PCM_FMTBIT_S20_3LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE) struct es8328_priv { struct regmap *regmap; struct clk *clk; int playback_fs; bool deemph; int mclkdiv2; const struct snd_pcm_hw_constraint_list *sysclk_constraints; const int *mclk_ratios; struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; }; Loading Loading @@ -439,54 +463,131 @@ static int es8328_mute(struct snd_soc_dai *dai, int mute) mute ? ES8328_DACCONTROL3_DACMUTE : 0); } static int es8328_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); if (es8328->sysclk_constraints) snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, es8328->sysclk_constraints); return 0; } static int es8328_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int clk_rate; int i; int reg; u8 ratio; int wl; int ratio; if (!es8328->sysclk_constraints) { dev_err(codec->dev, "No MCLK configured\n"); return -EINVAL; } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) reg = ES8328_DACCONTROL2; else reg = ES8328_ADCCONTROL5; clk_rate = clk_get_rate(es8328->clk); for (i = 0; i < es8328->sysclk_constraints->count; i++) if (es8328->sysclk_constraints->list[i] == params_rate(params)) break; if ((clk_rate != ES8328_SYSCLK_RATE_1X) && (clk_rate != ES8328_SYSCLK_RATE_2X)) { dev_err(codec->dev, "%s: clock is running at %d Hz, not %d or %d Hz\n", __func__, clk_rate, ES8328_SYSCLK_RATE_1X, ES8328_SYSCLK_RATE_2X); if (i == es8328->sysclk_constraints->count) { dev_err(codec->dev, "LRCLK %d unsupported with current clock\n", params_rate(params)); return -EINVAL; } /* find master mode MCLK to sampling frequency ratio */ ratio = mclk_ratios[0].rate; for (i = 1; i < ARRAY_SIZE(mclk_ratios); i++) if (params_rate(params) <= mclk_ratios[i].rate) ratio = mclk_ratios[i].ratio; ratio = es8328->mclk_ratios[i]; snd_soc_update_bits(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MCLKDIV2, es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); switch (params_width(params)) { case 16: wl = 3; break; case 18: wl = 2; break; case 20: wl = 1; break; case 24: wl = 0; break; case 32: wl = 4; break; default: return -EINVAL; } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { snd_soc_update_bits(codec, ES8328_DACCONTROL1, ES8328_DACCONTROL1_DACWL_MASK, wl << ES8328_DACCONTROL1_DACWL_SHIFT); es8328->playback_fs = params_rate(params); es8328_set_deemph(codec); } } else snd_soc_update_bits(codec, ES8328_ADCCONTROL4, ES8328_ADCCONTROL4_ADCWL_MASK, wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); return snd_soc_update_bits(codec, reg, ES8328_RATEMASK, ratio); } static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int mclkdiv2 = 0; switch (freq) { case 0: es8328->sysclk_constraints = NULL; es8328->mclk_ratios = NULL; break; case 22579200: mclkdiv2 = 1; /* fallthru */ case 11289600: es8328->sysclk_constraints = &constraints_11289; es8328->mclk_ratios = ratios_11289; break; case 24576000: mclkdiv2 = 1; /* fallthru */ case 12288000: es8328->sysclk_constraints = &constraints_12288; es8328->mclk_ratios = ratios_12288; break; default: return -EINVAL; } es8328->mclkdiv2 = mclkdiv2; return 0; } static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int clk_rate; u8 mode = ES8328_DACCONTROL1_DACWL_16; u8 dac_mode = 0; u8 adc_mode = 0; /* set master/slave audio interface */ if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM) Loading @@ -495,13 +596,16 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, /* interface format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; break; case SND_SOC_DAIFMT_RIGHT_J: mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; break; case SND_SOC_DAIFMT_LEFT_J: mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; break; default: return -EINVAL; Loading @@ -511,18 +615,14 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) return -EINVAL; snd_soc_write(codec, ES8328_DACCONTROL1, mode); snd_soc_write(codec, ES8328_ADCCONTROL4, mode); snd_soc_update_bits(codec, ES8328_DACCONTROL1, ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); snd_soc_update_bits(codec, ES8328_ADCCONTROL4, ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); /* Master serial port mode, with BCLK generated automatically */ clk_rate = clk_get_rate(es8328->clk); if (clk_rate == ES8328_SYSCLK_RATE_1X) snd_soc_write(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MSC); else snd_soc_write(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MCLKDIV2 | ES8328_MASTERMODE_MSC); snd_soc_update_bits(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MSC, ES8328_MASTERMODE_MSC); return 0; } Loading Loading @@ -579,8 +679,10 @@ static int es8328_set_bias_level(struct snd_soc_codec *codec, } static const struct snd_soc_dai_ops es8328_dai_ops = { .startup = es8328_startup, .hw_params = es8328_hw_params, .digital_mute = es8328_mute, .set_sysclk = es8328_set_sysclk, .set_fmt = es8328_set_dai_fmt, }; Loading @@ -601,6 +703,7 @@ static struct snd_soc_dai_driver es8328_dai = { .formats = ES8328_FORMATS, }, .ops = &es8328_dai_ops, .symmetric_rates = 1, }; static int es8328_suspend(struct snd_soc_codec *codec) Loading Loading @@ -708,6 +811,7 @@ const struct regmap_config es8328_regmap_config = { .val_bits = 8, .max_register = ES8328_REG_MAX, .cache_type = REGCACHE_RBTREE, .use_single_rw = true, }; EXPORT_SYMBOL_GPL(es8328_regmap_config); Loading Loading
Documentation/devicetree/bindings/sound/fsl-sai.txt +7 −2 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ codec/DSP interfaces. Required properties: - compatible : Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". - compatible : Compatible list, contains "fsl,vf610-sai", "fsl,imx6sx-sai" or "fsl,imx6ul-sai" - reg : Offset and length of the register set for the device. Loading Loading @@ -48,6 +48,11 @@ Required properties: receive data by following their own bit clocks and frame sync clocks separately. Optional properties (for mx6ul): - fsl,sai-mclk-direction-output: This is a boolean property. If present, indicates that SAI will output the SAI MCLK clock. Note: - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the default synchronous mode (sync Rx with Tx) will be used, which means both Loading
MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -4661,6 +4661,7 @@ FREESCALE SOC SOUND DRIVERS M: Timur Tabi <timur@tabi.org> M: Nicolin Chen <nicoleotsuka@gmail.com> M: Xiubo Li <Xiubo.Lee@gmail.com> R: Fabio Estevam <fabio.estevam@nxp.com> L: alsa-devel@alsa-project.org (moderated for non-subscribers) L: linuxppc-dev@lists.ozlabs.org S: Maintained Loading
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +6 −0 Original line number Diff line number Diff line Loading @@ -447,5 +447,11 @@ #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) #define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17) #define IMX6UL_GPR1_SAI1_MCLK_DIR (0x1 << 19) #define IMX6UL_GPR1_SAI2_MCLK_DIR (0x1 << 20) #define IMX6UL_GPR1_SAI3_MCLK_DIR (0x1 << 21) #define IMX6UL_GPR1_SAI_MCLK_MASK (0x7 << 19) #define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \ IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR) #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
include/sound/soc.h +3 −0 Original line number Diff line number Diff line Loading @@ -1683,6 +1683,9 @@ void snd_soc_remove_dai_link(struct snd_soc_card *card, int snd_soc_register_dai(struct snd_soc_component *component, struct snd_soc_dai_driver *dai_drv); struct snd_soc_dai *snd_soc_find_dai( const struct snd_soc_dai_link_component *dlc); #include <sound/soc-dai.h> #ifdef CONFIG_DEBUG_FS Loading
sound/soc/codecs/es8328.c +149 −45 Original line number Diff line number Diff line Loading @@ -26,18 +26,30 @@ #include <sound/tlv.h> #include "es8328.h" #define ES8328_SYSCLK_RATE_1X 11289600 #define ES8328_SYSCLK_RATE_2X 22579200 static const unsigned int rates_12288[] = { 8000, 12000, 16000, 24000, 32000, 48000, 96000, }; /* Run the codec at 22.5792 or 11.2896 MHz to support these rates */ static struct { int rate; u8 ratio; } mclk_ratios[] = { { 8000, 9 }, {11025, 7 }, {22050, 4 }, {44100, 2 }, static const int ratios_12288[] = { 10, 7, 6, 4, 3, 2, 0, }; static const struct snd_pcm_hw_constraint_list constraints_12288 = { .count = ARRAY_SIZE(rates_12288), .list = rates_12288, }; static const unsigned int rates_11289[] = { 8018, 11025, 22050, 44100, 88200, }; static const int ratios_11289[] = { 9, 7, 4, 2, 0, }; static const struct snd_pcm_hw_constraint_list constraints_11289 = { .count = ARRAY_SIZE(rates_11289), .list = rates_11289, }; /* regulator supplies for sgtl5000, VDDD is an optional external supply */ Loading @@ -57,16 +69,28 @@ static const char * const supply_names[ES8328_SUPPLY_NUM] = { "HPVDD", }; #define ES8328_RATES (SNDRV_PCM_RATE_44100 | \ #define ES8328_RATES (SNDRV_PCM_RATE_96000 | \ SNDRV_PCM_RATE_48000 | \ SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_32000 | \ SNDRV_PCM_RATE_22050 | \ SNDRV_PCM_RATE_11025) #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) SNDRV_PCM_RATE_16000 | \ SNDRV_PCM_RATE_11025 | \ SNDRV_PCM_RATE_8000) #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S18_3LE | \ SNDRV_PCM_FMTBIT_S20_3LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE) struct es8328_priv { struct regmap *regmap; struct clk *clk; int playback_fs; bool deemph; int mclkdiv2; const struct snd_pcm_hw_constraint_list *sysclk_constraints; const int *mclk_ratios; struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; }; Loading Loading @@ -439,54 +463,131 @@ static int es8328_mute(struct snd_soc_dai *dai, int mute) mute ? ES8328_DACCONTROL3_DACMUTE : 0); } static int es8328_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); if (es8328->sysclk_constraints) snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, es8328->sysclk_constraints); return 0; } static int es8328_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int clk_rate; int i; int reg; u8 ratio; int wl; int ratio; if (!es8328->sysclk_constraints) { dev_err(codec->dev, "No MCLK configured\n"); return -EINVAL; } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) reg = ES8328_DACCONTROL2; else reg = ES8328_ADCCONTROL5; clk_rate = clk_get_rate(es8328->clk); for (i = 0; i < es8328->sysclk_constraints->count; i++) if (es8328->sysclk_constraints->list[i] == params_rate(params)) break; if ((clk_rate != ES8328_SYSCLK_RATE_1X) && (clk_rate != ES8328_SYSCLK_RATE_2X)) { dev_err(codec->dev, "%s: clock is running at %d Hz, not %d or %d Hz\n", __func__, clk_rate, ES8328_SYSCLK_RATE_1X, ES8328_SYSCLK_RATE_2X); if (i == es8328->sysclk_constraints->count) { dev_err(codec->dev, "LRCLK %d unsupported with current clock\n", params_rate(params)); return -EINVAL; } /* find master mode MCLK to sampling frequency ratio */ ratio = mclk_ratios[0].rate; for (i = 1; i < ARRAY_SIZE(mclk_ratios); i++) if (params_rate(params) <= mclk_ratios[i].rate) ratio = mclk_ratios[i].ratio; ratio = es8328->mclk_ratios[i]; snd_soc_update_bits(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MCLKDIV2, es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); switch (params_width(params)) { case 16: wl = 3; break; case 18: wl = 2; break; case 20: wl = 1; break; case 24: wl = 0; break; case 32: wl = 4; break; default: return -EINVAL; } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { snd_soc_update_bits(codec, ES8328_DACCONTROL1, ES8328_DACCONTROL1_DACWL_MASK, wl << ES8328_DACCONTROL1_DACWL_SHIFT); es8328->playback_fs = params_rate(params); es8328_set_deemph(codec); } } else snd_soc_update_bits(codec, ES8328_ADCCONTROL4, ES8328_ADCCONTROL4_ADCWL_MASK, wl << ES8328_ADCCONTROL4_ADCWL_SHIFT); return snd_soc_update_bits(codec, reg, ES8328_RATEMASK, ratio); } static int es8328_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int mclkdiv2 = 0; switch (freq) { case 0: es8328->sysclk_constraints = NULL; es8328->mclk_ratios = NULL; break; case 22579200: mclkdiv2 = 1; /* fallthru */ case 11289600: es8328->sysclk_constraints = &constraints_11289; es8328->mclk_ratios = ratios_11289; break; case 24576000: mclkdiv2 = 1; /* fallthru */ case 12288000: es8328->sysclk_constraints = &constraints_12288; es8328->mclk_ratios = ratios_12288; break; default: return -EINVAL; } es8328->mclkdiv2 = mclkdiv2; return 0; } static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); int clk_rate; u8 mode = ES8328_DACCONTROL1_DACWL_16; u8 dac_mode = 0; u8 adc_mode = 0; /* set master/slave audio interface */ if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM) Loading @@ -495,13 +596,16 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, /* interface format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S; break; case SND_SOC_DAIFMT_RIGHT_J: mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST; break; case SND_SOC_DAIFMT_LEFT_J: mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST; break; default: return -EINVAL; Loading @@ -511,18 +615,14 @@ static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) return -EINVAL; snd_soc_write(codec, ES8328_DACCONTROL1, mode); snd_soc_write(codec, ES8328_ADCCONTROL4, mode); snd_soc_update_bits(codec, ES8328_DACCONTROL1, ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode); snd_soc_update_bits(codec, ES8328_ADCCONTROL4, ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode); /* Master serial port mode, with BCLK generated automatically */ clk_rate = clk_get_rate(es8328->clk); if (clk_rate == ES8328_SYSCLK_RATE_1X) snd_soc_write(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MSC); else snd_soc_write(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MCLKDIV2 | ES8328_MASTERMODE_MSC); snd_soc_update_bits(codec, ES8328_MASTERMODE, ES8328_MASTERMODE_MSC, ES8328_MASTERMODE_MSC); return 0; } Loading Loading @@ -579,8 +679,10 @@ static int es8328_set_bias_level(struct snd_soc_codec *codec, } static const struct snd_soc_dai_ops es8328_dai_ops = { .startup = es8328_startup, .hw_params = es8328_hw_params, .digital_mute = es8328_mute, .set_sysclk = es8328_set_sysclk, .set_fmt = es8328_set_dai_fmt, }; Loading @@ -601,6 +703,7 @@ static struct snd_soc_dai_driver es8328_dai = { .formats = ES8328_FORMATS, }, .ops = &es8328_dai_ops, .symmetric_rates = 1, }; static int es8328_suspend(struct snd_soc_codec *codec) Loading Loading @@ -708,6 +811,7 @@ const struct regmap_config es8328_regmap_config = { .val_bits = 8, .max_register = ES8328_REG_MAX, .cache_type = REGCACHE_RBTREE, .use_single_rw = true, }; EXPORT_SYMBOL_GPL(es8328_regmap_config); Loading