Commit 17fc14ff authored by Jacob Shin's avatar Jacob Shin Committed by Linus Torvalds
Browse files

[PATCH] x86_64: apic support for extended apic interrupt 



Add support for extended APIC LVT found in future AMD processors.

Signed-off-by: default avatarJacob Shin <jacob.shin@amd.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent c38bfdc8

arch/x86_64/kernel/apic.c

+4 −6
Original line number Diff line number Diff line
@@ -909,15 +909,13 @@ int setup_profiling_timer(unsigned int multiplier) 
	return -EINVAL;

}



#ifdef CONFIG_X86_MCE_AMD

void setup_threshold_lvt(unsigned long lvt_off)

void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector,

			    unsigned char msg_type, unsigned char mask)

{

	unsigned int v = 0;

	unsigned long reg = (lvt_off << 4) + 0x500;

	v |= THRESHOLD_APIC_VECTOR;

	unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;

	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;

	apic_write(reg, v);

}

#endif /* CONFIG_X86_MCE_AMD */



#undef APIC_DIVISOR

include/asm-x86_64/apic.h

+10 −1
Original line number Diff line number Diff line
@@ -84,9 +84,18 @@ extern void disable_APIC_timer(void); 
extern void enable_APIC_timer(void);

extern void clustered_apic_check(void);



extern void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector,

				   unsigned char msg_type, unsigned char mask);



#define K8_APIC_EXT_LVT_BASE    0x500

#define K8_APIC_EXT_INT_MSG_FIX 0x0

#define K8_APIC_EXT_INT_MSG_SMI 0x2

#define K8_APIC_EXT_INT_MSG_NMI 0x4

#define K8_APIC_EXT_INT_MSG_EXT 0x7

#define K8_APIC_EXT_LVT_ENTRY_THRESHOLD    0



extern int disable_timer_pin_1;



extern void setup_threshold_lvt(unsigned long lvt_off);



void smp_send_timer_broadcast_ipi(void);

void switch_APIC_timer_to_ipi(void *cpumask);