Commit 17f8fc19 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "We've got a smattering of changes all over the place which we've
  acrued since -rc1. To my knowledge, there aren't any pending issues at
  the moment, but there's still plenty of time for something else to
  crop up...

  Summary:

   - Fix booting a 52-bit-VA-aware kernel on Qualcomm Amberwing

   - Fix pfn_valid() not to reject all ZONE_DEVICE memory

   - Fix memory tagging setup for hotplugged memory regions

   - Fix KASAN tagging in page_alloc() when DEBUG_VIRTUAL is enabled

   - Fix accidental truncation of CPU PMU event counters

   - Fix error code initialisation when failing probe of DMC620 PMU

   - Fix return value initialisation for sve-ptrace selftest

   - Drop broken support for CMDLINE_EXTEND"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  perf/arm_dmc620_pmu: Fix error return code in dmc620_pmu_device_probe()
  arm64: mm: remove unused __cpu_uses_extended_idmap[_level()]
  arm64: mm: use a 48-bit ID map when possible on 52-bit VA builds
  arm64: perf: Fix 64-bit event counter read truncation
  arm64/mm: Fix __enable_mmu() for new TGRAN range values
  kselftest: arm64: Fix exit code of sve-ptrace
  arm64: mte: Map hotplugged memory as Normal Tagged
  arm64: kasan: fix page_alloc tagging with DEBUG_VIRTUAL
  arm64/mm: Reorganize pfn_valid()
  arm64/mm: Fix pfn_valid() for ZONE_DEVICE based memory
  arm64/mm: Drop THP conditionality from FORCE_MAX_ZONEORDER
  arm64/mm: Drop redundant ARCH_WANT_HUGE_PMD_SHARE
  arm64: Drop support for CMDLINE_EXTEND
  arm64: cpufeatures: Fix handling of CONFIG_CMDLINE for idreg overrides
parents 6bf8819f c8e38668

arch/arm64/Kconfig

+2 −10
Original line number Diff line number Diff line
@@ -1055,8 +1055,6 @@ config HW_PERF_EVENTS 
config SYS_SUPPORTS_HUGETLBFS

	def_bool y



config ARCH_WANT_HUGE_PMD_SHARE



config ARCH_HAS_CACHE_LINE_SIZE

	def_bool y
@@ -1157,8 +1155,8 @@ config XEN 


config FORCE_MAX_ZONEORDER

	int

	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)

	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)

	default "14" if ARM64_64K_PAGES

	default "12" if ARM64_16K_PAGES

	default "11"

	help

	  The kernel memory allocator divides physically contiguous memory
@@ -1855,12 +1853,6 @@ config CMDLINE_FROM_BOOTLOADER 
	  the boot loader doesn't provide any, the default kernel command

	  string provided in CMDLINE will be used.



config CMDLINE_EXTEND

	bool "Extend bootloader kernel arguments"

	help

	  The command-line arguments provided by the boot loader will be

	  appended to the default kernel command string.



config CMDLINE_FORCE

	bool "Always use the default kernel command string"

	help

arch/arm64/include/asm/memory.h

+5 −0
Original line number Diff line number Diff line
@@ -328,6 +328,11 @@ static inline void *phys_to_virt(phys_addr_t x) 
#define ARCH_PFN_OFFSET		((unsigned long)PHYS_PFN_OFFSET)



#if !defined(CONFIG_SPARSEMEM_VMEMMAP) || defined(CONFIG_DEBUG_VIRTUAL)

#define page_to_virt(x)	({						\

	__typeof__(x) __page = x;					\

	void *__addr = __va(page_to_phys(__page));			\

	(void *)__tag_set((const void *)__addr, page_kasan_tag(__page));\

})

#define virt_to_page(x)		pfn_to_page(virt_to_pfn(x))

#else

#define page_to_virt(x)	({						\

arch/arm64/include/asm/mmu_context.h

+0 −17
Original line number Diff line number Diff line
@@ -63,23 +63,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 
extern u64 idmap_t0sz;

extern u64 idmap_ptrs_per_pgd;



static inline bool __cpu_uses_extended_idmap(void)

{

	if (IS_ENABLED(CONFIG_ARM64_VA_BITS_52))

		return false;



	return unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS));

}



/*

 * True if the extended ID map requires an extra level of translation table

 * to be configured.

 */

static inline bool __cpu_uses_extended_idmap_level(void)

{

	return ARM64_HW_PGTABLE_LEVELS(64 - idmap_t0sz) > CONFIG_PGTABLE_LEVELS;

}



/*

 * Ensure TCR.T0SZ is set to the provided value.

 */

arch/arm64/include/asm/pgtable-prot.h

+0 −1
Original line number Diff line number Diff line
@@ -66,7 +66,6 @@ extern bool arm64_use_ng_mappings; 
#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))



#define PAGE_KERNEL		__pgprot(PROT_NORMAL)

#define PAGE_KERNEL_TAGGED	__pgprot(PROT_NORMAL_TAGGED)

#define PAGE_KERNEL_RO		__pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)

#define PAGE_KERNEL_ROX		__pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)

#define PAGE_KERNEL_EXEC	__pgprot(PROT_NORMAL & ~PTE_PXN)

arch/arm64/include/asm/pgtable.h

+3 −0
Original line number Diff line number Diff line
@@ -486,6 +486,9 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) 
	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)

#define pgprot_device(prot) \

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)

#define pgprot_tagged(prot) \

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))

#define pgprot_mhp	pgprot_tagged

/*

 * DMA allocations for non-coherent devices use what the Arm architecture calls

 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses