Commit 1792bdac authored Jul 14, 2021 by Martin Blumenstingl Committed by Jerome Brunet Sep 23, 2021

clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel

Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only
parent which is actually used is vid_pll_final_div. This should be set
using assigned-clock-parents in the .dts rather than removing some
"unwanted" clock parents from the clock driver.

Suggested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-2-martin.blumenstingl@googlemail.com

parent 2e120542

drivers/clk/meson/meson8b.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1175,7 +1175,7 @@ static struct clk_regmap meson8b_vclk_in_sel = {
		.ops = &clk_regmap_mux_ro_ops,
		.parent_hws = meson8b_vclk_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
		},
		};

		@@ -1358,7 +1358,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
		.ops = &clk_regmap_mux_ro_ops,
		.parent_hws = meson8b_vclk_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
		},
		};