Commit 1775634e authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update Intel broadwell 

Update to v26, the metrics are based on TMA 4.4 full.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



to download and generate the latest events and metrics. Manually copy
the broadwell files into perf and update mapfile.csv.

Tested on a non-broadwell with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-3-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4266081e

tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json

+83 −47
Original line number Diff line number Diff line
@@ -130,43 +130,25 @@ 
        "MetricName": "FLOPc_SMT"

    },

    {

        "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",

        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",

        "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",

        "MetricGroup": "Cor;Flops;HPC",

        "MetricName": "FP_Arith_Utilization",

        "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."

        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."

    },

    {

        "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",

        "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). SMT version; use when SMT is enabled and measuring per logical CPU.",

        "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",

        "MetricGroup": "Cor;Flops;HPC_SMT",

        "MetricName": "FP_Arith_Utilization_SMT",

        "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."

        "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common). SMT version; use when SMT is enabled and measuring per logical CPU."

    },

    {

        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",

        "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",

        "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",

        "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",

        "MetricName": "ILP"

    },

    {

        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",

        "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BrMispredicts",

        "MetricName": "Branch_Misprediction_Cost"

    },

    {

        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",

        "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BrMispredicts_SMT",

        "MetricName": "Branch_Misprediction_Cost_SMT"

    },

    {

        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",

        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BadSpec;BrMispredicts",

        "MetricName": "IpMispredict"

    },

    {

        "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",

        "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
@@ -256,6 +238,18 @@ 
        "MetricGroup": "Summary;TmaL1",

        "MetricName": "Instructions"

    },

    {

        "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",

        "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",

        "MetricGroup": "Pipeline;Ret",

        "MetricName": "Retire"

    },

    {

        "BriefDescription": "",

        "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",

        "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",

        "MetricName": "Execute"

    },

    {

        "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",

        "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
@@ -263,35 +257,34 @@ 
        "MetricName": "DSB_Coverage"

    },

    {

        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",

        "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",

        "MetricGroup": "Mem;MemoryBound;MemoryLat",

        "MetricName": "Load_Miss_Real_Latency",

        "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."

        "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",

        "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BadSpec;BrMispredicts",

        "MetricName": "IpMispredict"

    },

    {

        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",

        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",

        "MetricGroup": "Mem;MemoryBound;MemoryBW",

        "MetricName": "MLP"

        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",

        "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BrMispredicts",

        "MetricName": "Branch_Misprediction_Cost"

    },

    {

        "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",

        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L1D_Cache_Fill_BW"

        "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",

        "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",

        "MetricGroup": "Bad;BrMispredicts_SMT",

        "MetricName": "Branch_Misprediction_Cost_SMT"

    },

    {

        "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",

        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L2_Cache_Fill_BW"

        "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",

        "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",

        "MetricGroup": "Mem;MemoryBound;MemoryLat",

        "MetricName": "Load_Miss_Real_Latency"

    },

    {

        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",

        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L3_Cache_Fill_BW"

        "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",

        "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",

        "MetricGroup": "Mem;MemoryBound;MemoryBW",

        "MetricName": "MLP"

    },

    {

        "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
@@ -306,13 +299,13 @@ 
        "MetricName": "L2MPKI"

    },

    {

        "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",

        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",

        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",

        "MetricGroup": "Mem;CacheMisses;Offcore",

        "MetricName": "L2MPKI_All"

    },

    {

        "BriefDescription": "L2 cache misses per kilo instruction for all demand loads  (including speculative)",

        "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",

        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",

        "MetricGroup": "Mem;CacheMisses",

        "MetricName": "L2MPKI_Load"
@@ -348,6 +341,48 @@ 
        "MetricGroup": "Mem;MemoryTLB_SMT",

        "MetricName": "Page_Walks_Utilization_SMT"

    },

    {

        "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",

        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L1D_Cache_Fill_BW"

    },

    {

        "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",

        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L2_Cache_Fill_BW"

    },

    {

        "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",

        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L3_Cache_Fill_BW"

    },

    {

        "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",

        "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L1D_Cache_Fill_BW_1T"

    },

    {

        "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",

        "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L2_Cache_Fill_BW_1T"

    },

    {

        "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",

        "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",

        "MetricGroup": "Mem;MemoryBW",

        "MetricName": "L3_Cache_Fill_BW_1T"

    },

    {

        "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",

        "MetricExpr": "0",

        "MetricGroup": "Mem;MemoryBW;Offcore",

        "MetricName": "L3_Cache_Access_BW_1T"

    },

    {

        "BriefDescription": "Average CPU Utilization",

        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
@@ -364,7 +399,8 @@ 
        "BriefDescription": "Giga Floating Point Operations Per Second",

        "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",

        "MetricGroup": "Cor;Flops;HPC",

        "MetricName": "GFLOPs"

        "MetricName": "GFLOPs",

        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."

    },

    {

        "BriefDescription": "Average Frequency Utilization relative nominal frequency",

tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json

0 → 100644
+152 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",

        "UMask": "0x86",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",

        "UMask": "0x88",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",

        "UMask": "0x81",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",

        "UMask": "0x8f",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",

        "UMask": "0x16",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",

        "UMask": "0x18",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",

        "UMask": "0x11",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",

        "UMask": "0x1f",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",

        "UMask": "0x26",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",

        "UMask": "0x21",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",

        "Counter": "0,1",

        "EventCode": "0x34",

        "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",

        "PerPkg": "1",

        "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",

        "UMask": "0x2f",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

        "Counter": "0,1",

        "EventCode": "0x22",

        "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",

        "PerPkg": "1",

        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

        "UMask": "0x48",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

        "Counter": "0,1",

        "EventCode": "0x22",

        "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",

        "PerPkg": "1",

        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

        "UMask": "0x44",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

        "Counter": "0,1",

        "EventCode": "0x22",

        "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",

        "PerPkg": "1",

        "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

        "UMask": "0x81",

        "Unit": "CBO"

    },

    {

        "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

        "Counter": "0,1",

        "EventCode": "0x22",

        "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",

        "PerPkg": "1",

        "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

        "UMask": "0x41",

        "Unit": "CBO"

    }

]

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