Unverified Commit 176b28d6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4484 v4 Using smmu IIDR registers 

Merge Pull Request from: @ci-robot 
 
PR sync from: Zhang Zekun <zhangzekun11@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/L6K7LNVFBRLIXAGKCLBSCUURRFY3WSUW/ 
Using the smmu registers to identify the problem described
in commit 8544c8e1 ("iommu/arm-smmu-v3: Add a SYNC command
to avoid broken page table prefetch").

v2:
Remove the commit message spell error.

v3:
Revert the previous patch and using a brand new patch instead.

v4:
Fix a judge error and change the commit message.

Zhang Zekun (2):
  Revert "iommu/arm-smmu-v3: Add a SYNC command to avoid broken page
    table prefetch"
  iommu/arm-smmu-v3: Enable iotlb_sync_map according to SMMU_IIDR


-- 
2.17.1
 
https://gitee.com/src-openeuler/kernel/issues/I913T5 
 
Link:https://gitee.com/openeuler/kernel/pulls/4484

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarWeilong Chen <chenweilong@huawei.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 30dc7d25 46f0c579

Documentation/arm64/silicon-errata.rst

+1 −1
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100602      | HISILICON_ERRATUM_162100602 |

| Hisilicon      | SMMUv3          | #162100602      | HISILICON_ERRATUM_162100602 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | HIP09           | #162102203      | HISILICON_ERRATUM_162102203 |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+6 −7
Original line number Diff line number Diff line
@@ -838,14 +838,13 @@ config HISILICON_ERRATUM_162102203 


config HISILICON_ERRATUM_162100602

	bool "Hisilicon erratum 162100602"

	depends on ARM_SMMU_V3

	depends on ARM_SMMU_V3 && ARCH_HISI

	default y

	help

	 On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may

	 prefetch and use a invalid PTE even the PTE is valid at that time. This

	 will cause the device trigger fake pagefaults. If the SMMU works in

	 terminate mode, transactions which occur fake pagefaults will be aborted,

	 and could result in unexpected errors.

	  SMMU pagetable prefetch features may prefetch and use a invalid PTE even

	  the PTE is valid at that time. This will cause the device trigger fake

	  pagefaults. If the SMMU works in terminate mode, transactions which occur

	  fake pagefaults will be aborted, and could result in unexpected errors.



	  If unsure, say Y.

arch/arm64/include/asm/cpucaps.h

+0 −1
Original line number Diff line number Diff line
@@ -81,7 +81,6 @@ 
#define ARM64_HAS_PBHA_STAGE2			73

#define ARM64_SME				74

#define ARM64_SME_FA64				75

#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602	76



#define ARM64_NCAPS				80

arch/arm64/kernel/cpu_errata.c

+0 −14
Original line number Diff line number Diff line
@@ -331,13 +331,6 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { 
};

#endif



#ifdef CONFIG_HISILICON_ERRATUM_162100602

static const struct midr_range hisilicon_erratum_162100602_cpus[] = {

	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),

	{},

};

#endif



#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {

	{
@@ -540,13 +533,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_162100602

	{

		.desc = "Hisilicon erratum 162100602",

		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602,

		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus),

	},

#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

	{

		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+9 −1
Original line number Diff line number Diff line
@@ -2948,7 +2948,7 @@ static void arm_smmu_iotlb_sync_map(struct iommu_domain *domain, 
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	size_t granule_size;



	if (!cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100602))

	if (!(smmu_domain->smmu->options & ARM_SMMU_OPT_SYNC_MAP))

		return;



	granule_size = 1 <<  __ffs(smmu_domain->domain.pgsize_bitmap);
@@ -5146,6 +5146,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) 
		smmu->oas = 48;

	}



#ifdef CONFIG_HISILICON_ERRATUM_162100602

	/* IIDR */

	reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR);

	if (FIELD_GET(IIDR_VARIANT, reg) == 0x3 &&

	    FIELD_GET(IIDR_REVISON, reg) == 0x2)

		smmu->options |= ARM_SMMU_OPT_SYNC_MAP;

#endif



	if (arm_smmu_ops.pgsize_bitmap == -1UL)

		arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;

	else