Commit 17179d00 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-fixes-5.17-1' of... 

Merge tag 'kvmarm-fixes-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 fixes for 5.17, take #1

- Correctly update the shadow register on exception injection when
  running in nVHE mode

- Correctly use the mm_ops indirection when performing cache invalidation
  from the page-table walker

- Restrict the vgic-v3 workaround for SEIS to the two known broken
  implementations
parents 6a0c6170 27858305

arch/arm64/kvm/hyp/exception.c

+4 −1
Original line number Diff line number Diff line
@@ -38,7 +38,10 @@ static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 


static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, u64 val)

{

	if (has_vhe())

		write_sysreg_el1(val, SYS_SPSR);

	else

		__vcpu_sys_reg(vcpu, SPSR_EL1) = val;

}



static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val)

arch/arm64/kvm/hyp/pgtable.c

+6 −12
Original line number Diff line number Diff line
@@ -983,13 +983,9 @@ static int stage2_unmap_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, 
	 */

	stage2_put_pte(ptep, mmu, addr, level, mm_ops);



	if (need_flush) {

		kvm_pte_t *pte_follow = kvm_pte_follow(pte, mm_ops);



		dcache_clean_inval_poc((unsigned long)pte_follow,

				    (unsigned long)pte_follow +

	if (need_flush && mm_ops->dcache_clean_inval_poc)

		mm_ops->dcache_clean_inval_poc(kvm_pte_follow(pte, mm_ops),

					       kvm_granule_size(level));

	}



	if (childp)

		mm_ops->put_page(childp);
@@ -1151,14 +1147,12 @@ static int stage2_flush_walker(u64 addr, u64 end, u32 level, kvm_pte_t *ptep, 
	struct kvm_pgtable *pgt = arg;

	struct kvm_pgtable_mm_ops *mm_ops = pgt->mm_ops;

	kvm_pte_t pte = *ptep;

	kvm_pte_t *pte_follow;



	if (!kvm_pte_valid(pte) || !stage2_pte_cacheable(pgt, pte))

		return 0;



	pte_follow = kvm_pte_follow(pte, mm_ops);

	dcache_clean_inval_poc((unsigned long)pte_follow,

			    (unsigned long)pte_follow +

	if (mm_ops->dcache_clean_inval_poc)

		mm_ops->dcache_clean_inval_poc(kvm_pte_follow(pte, mm_ops),

					       kvm_granule_size(level));

	return 0;

}

arch/arm64/kvm/hyp/vgic-v3-sr.c

+3 −0
Original line number Diff line number Diff line
@@ -983,6 +983,9 @@ static void __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) 
	val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;

	/* IDbits */

	val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;

	/* SEIS */

	if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK)

		val |= BIT(ICC_CTLR_EL1_SEIS_SHIFT);

	/* A3V */

	val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;

	/* EOImode */

arch/arm64/kvm/vgic/vgic-v3.c

+15 −2
Original line number Diff line number Diff line
@@ -609,6 +609,18 @@ static int __init early_gicv4_enable(char *buf) 
}

early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);



static const struct midr_range broken_seis[] = {

	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),

	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),

	{},

};



static bool vgic_v3_broken_seis(void)

{

	return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&

		is_midr_in_range_list(read_cpuid_id(), broken_seis));

}



/**

 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller

 * @info:	pointer to the GIC description
@@ -676,9 +688,10 @@ int vgic_v3_probe(const struct gic_kvm_info *info) 
		group1_trap = true;

	}



	if (kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) {

		kvm_info("GICv3 with locally generated SEI\n");

	if (vgic_v3_broken_seis()) {

		kvm_info("GICv3 with broken locally generated SEI\n");



		kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;

		group0_trap = true;

		group1_trap = true;

		if (ich_vtr_el2 & ICH_VTR_TDS_MASK)