Unverified Commit 16e769e2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.17-next-soc' of... 

Merge tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

- add power domains support for mt8195
- disable ACP on mt8192

mt8186:
- add support for power domains
- add mmsys and mutex support needed for DRM
- add reset control based on mmsys subsystem
- add pmic wrapper

* tag 'v5.17-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  dt-bindings: arm: mediatek: mmsys: add support for MT8186
  dt-bindings: mediatek: add compatible for MT8186 pwrap
  soc: mediatek: pwrap: add pwrap driver for MT8186 SoC
  soc: mediatek: mmsys: add mmsys reset control for MT8186
  soc: mediatek: mtk-infracfg: Disable ACP on MT8192
  soc: mediatek: add MTK mutex support for MT8186
  soc: mediatek: mmsys: add mt8186 mmsys routing table
  soc: mediatek: pm-domains: Add support for mt8186
  dt-bindings: power: Add MT8186 power domains
  soc: mediatek: pm-domains: Add support for mt8195
  soc: mediatek: pm-domains: Move power status offset to power domain data
  soc: mediatek: pm-domains: Remove unused macro
  soc: mediatek: pm-domains: Add wakeup capacity support in power domain
  dt-bindings: power: Add MT8195 power domains

Link: https://lore.kernel.org/r/16a53482-5a8c-e95e-8cd4-b8304f110987@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 42ba4173 eb1b02be

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ properties: 
              - mediatek,mt8167-mmsys

              - mediatek,mt8173-mmsys

              - mediatek,mt8183-mmsys

              - mediatek,mt8186-mmsys

              - mediatek,mt8192-mmsys

              - mediatek,mt8365-mmsys

          - const: syscon

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

+3 −0
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ properties: 
      - mediatek,mt8167-power-controller

      - mediatek,mt8173-power-controller

      - mediatek,mt8183-power-controller

      - mediatek,mt8186-power-controller

      - mediatek,mt8192-power-controller

      - mediatek,mt8195-power-controller



  '#power-domain-cells':

    const: 1
@@ -64,6 +66,7 @@ patternProperties: 
              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.

              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.

              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.

              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.

        maxItems: 1



      clocks:

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ Required properties in pwrap device node. 
	"mediatek,mt8135-pwrap" for MT8135 SoCs

	"mediatek,mt8173-pwrap" for MT8173 SoCs

	"mediatek,mt8183-pwrap" for MT8183 SoCs

	"mediatek,mt8186-pwrap" for MT8186 SoCs

	"mediatek,mt8195-pwrap" for MT8195 SoCs

	"mediatek,mt8516-pwrap" for MT8516 SoCs

- interrupts: IRQ for pwrap in SOC

drivers/soc/mediatek/mt8167-pm-domains.h

+14 −2
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "mm",

		.sta_mask = PWR_STATUS_DISP,

		.ctl_offs = SPM_DIS_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {
@@ -30,6 +32,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "vdec",

		.sta_mask = PWR_STATUS_VDEC,

		.ctl_offs = SPM_VDE_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.caps = MTK_SCPD_ACTIVE_WAKEUP,
@@ -38,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "isp",

		.sta_mask = PWR_STATUS_ISP,

		.ctl_offs = SPM_ISP_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.caps = MTK_SCPD_ACTIVE_WAKEUP,
@@ -46,6 +52,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "mfg_async",

		.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,

		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = 0,

		.sram_pdn_ack_bits = 0,

		.bp_infracfg = {
@@ -57,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "mfg_2d",

		.sta_mask = MT8167_PWR_STATUS_MFG_2D,

		.ctl_offs = SPM_MFG_2D_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},
@@ -64,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "mfg",

		.sta_mask = PWR_STATUS_MFG,

		.ctl_offs = SPM_MFG_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},
@@ -71,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.name = "conn",

		.sta_mask = PWR_STATUS_CONN,

		.ctl_offs = SPM_CONN_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = 0,

		.caps = MTK_SCPD_ACTIVE_WAKEUP,
@@ -85,8 +99,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
static const struct scpsys_soc_data mt8167_scpsys_data = {

	.domains_data = scpsys_domain_data_mt8167,

	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),

	.pwr_sta_offs = SPM_PWR_STATUS,

	.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

};



#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */

drivers/soc/mediatek/mt8173-pm-domains.h

+20 −2
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "vdec",

		.sta_mask = PWR_STATUS_VDEC,

		.ctl_offs = SPM_VDE_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

	},
@@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "venc",

		.sta_mask = PWR_STATUS_VENC,

		.ctl_offs = SPM_VEN_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},
@@ -29,6 +33,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "isp",

		.sta_mask = PWR_STATUS_ISP,

		.ctl_offs = SPM_ISP_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

	},
@@ -36,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "mm",

		.sta_mask = PWR_STATUS_DISP,

		.ctl_offs = SPM_DIS_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.bp_infracfg = {
@@ -47,6 +55,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "venc_lt",

		.sta_mask = PWR_STATUS_VENC_LT,

		.ctl_offs = SPM_VEN2_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},
@@ -54,6 +64,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "audio",

		.sta_mask = PWR_STATUS_AUDIO,

		.ctl_offs = SPM_AUDIO_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},
@@ -61,6 +73,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "usb",

		.sta_mask = PWR_STATUS_USB,

		.ctl_offs = SPM_USB_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.caps = MTK_SCPD_ACTIVE_WAKEUP,
@@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "mfg_async",

		.sta_mask = PWR_STATUS_MFG_ASYNC,

		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = 0,

		.caps = MTK_SCPD_DOMAIN_SUPPLY,
@@ -77,6 +93,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "mfg_2d",

		.sta_mask = PWR_STATUS_MFG_2D,

		.ctl_offs = SPM_MFG_2D_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

	},
@@ -84,6 +102,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.name = "mfg",

		.sta_mask = PWR_STATUS_MFG,

		.ctl_offs = SPM_MFG_PWR_CON,

		.pwr_sta_offs = SPM_PWR_STATUS,

		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

		.sram_pdn_bits = GENMASK(13, 8),

		.sram_pdn_ack_bits = GENMASK(21, 16),

		.bp_infracfg = {
@@ -98,8 +118,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
static const struct scpsys_soc_data mt8173_scpsys_data = {

	.domains_data = scpsys_domain_data_mt8173,

	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),

	.pwr_sta_offs = SPM_PWR_STATUS,

	.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,

};



#endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */