Unverified Commit 16b22f85 authored by Paul Burton's avatar Paul Burton
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Revert "MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices" 

Commit e6046b5e ("MIPS: ralink: fix cpu clock of mt7621 and add dt
clk devices") includes a file that doesn't exist, causing build
failures... Revert it.

References: https://lore.kernel.org/linux-mips/CAJsYDVJvviz8a2oVmb0XL3OB+=Eecu-3kC9T9vsmxpuC_BqDSA@mail.gmail.com/


Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
parent 3e3d1dfd

arch/mips/include/asm/mach-ralink/mt7621.h

+0 −20
Original line number Diff line number Diff line
@@ -19,10 +19,6 @@ 
#define SYSC_REG_CHIP_REV		0x0c

#define SYSC_REG_SYSTEM_CONFIG0		0x10

#define SYSC_REG_SYSTEM_CONFIG1		0x14

#define SYSC_REG_CLKCFG0		0x2c

#define SYSC_REG_CUR_CLK_STS		0x44



#define MEMC_REG_CPU_PLL		0x648



#define CHIP_REV_PKG_MASK		0x1

#define CHIP_REV_PKG_SHIFT		16
@@ -30,22 +26,6 @@ 
#define CHIP_REV_VER_SHIFT		8

#define CHIP_REV_ECO_MASK		0xf



#define XTAL_MODE_SEL_MASK		0x7

#define XTAL_MODE_SEL_SHIFT		6



#define CPU_CLK_SEL_MASK		0x3

#define CPU_CLK_SEL_SHIFT		30



#define CUR_CPU_FDIV_MASK		0x1f

#define CUR_CPU_FDIV_SHIFT		8

#define CUR_CPU_FFRAC_MASK		0x1f

#define CUR_CPU_FFRAC_SHIFT		0



#define CPU_PLL_PREDIV_MASK		0x3

#define CPU_PLL_PREDIV_SHIFT		12

#define CPU_PLL_FBDIV_MASK		0x7f

#define CPU_PLL_FBDIV_SHIFT		4



#define MT7621_DRAM_BASE                0x0

#define MT7621_DDR2_SIZE_MIN		32

#define MT7621_DDR2_SIZE_MAX		256

arch/mips/ralink/mt7621.c

+31 −71
Original line number Diff line number Diff line
@@ -9,22 +9,22 @@ 


#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/clk.h>

#include <linux/clkdev.h>

#include <linux/clk-provider.h>

#include <dt-bindings/clock/mt7621-clk.h>



#include <asm/mipsregs.h>

#include <asm/smp-ops.h>

#include <asm/mips-cps.h>

#include <asm/mach-ralink/ralink_regs.h>

#include <asm/mach-ralink/mt7621.h>

#include <asm/time.h>



#include <pinmux.h>



#include "common.h"



#define SYSC_REG_SYSCFG		0x10

#define SYSC_REG_CPLL_CLKCFG0	0x2c

#define SYSC_REG_CUR_CLK_STS	0x44

#define CPU_CLK_SEL		(BIT(30) | BIT(31))



#define MT7621_GPIO_MODE_UART1		1

#define MT7621_GPIO_MODE_I2C		2

#define MT7621_GPIO_MODE_UART3_MASK	0x3
@@ -110,89 +110,49 @@ static struct rt2880_pmx_group mt7621_pinmux_data[] = { 
	{ 0 }

};



static struct clk *clks[MT7621_CLK_MAX];

static struct clk_onecell_data clk_data = {

	.clks = clks,

	.clk_num = ARRAY_SIZE(clks),

};



phys_addr_t mips_cpc_default_phys_base(void)

{

	panic("Cannot detect cpc address");

}



static struct clk *__init mt7621_add_sys_clkdev(

	const char *id, unsigned long rate)

{

	struct clk *clk;

	int err;



	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);

	if (IS_ERR(clk))

		panic("failed to allocate %s clock structure", id);



	err = clk_register_clkdev(clk, id, NULL);

	if (err)

		panic("unable to register %s clock device", id);



	return clk;

}



void __init ralink_clk_init(void)

{

	const static u32 prediv_tbl[] = {0, 1, 2, 2};

	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;

	u32 pll, prediv, fbdiv;

	u32 xtal_clk, cpu_clk, bus_clk;



	syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);

	xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;



	clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);

	clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;

	int cpu_fdiv = 0;

	int cpu_ffrac = 0;

	int fbdiv = 0;

	u32 clk_sts, syscfg;

	u8 clk_sel = 0, xtal_mode;

	u32 cpu_clk;



	curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);

	ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;

	ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;



	if (xtal_sel <= 2)

		xtal_clk = 20 * 1000 * 1000;

	else if (xtal_sel <= 5)

		xtal_clk = 40 * 1000 * 1000;

	else

		xtal_clk = 25 * 1000 * 1000;

	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)

		clk_sel = 1;



	switch (clk_sel) {

	case 0:

		cpu_clk = 500 * 1000 * 1000;

		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);

		cpu_fdiv = ((clk_sts >> 8) & 0x1F);

		cpu_ffrac = (clk_sts & 0x1F);

		cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;

		break;



	case 1:

		pll = rt_memc_r32(MEMC_REG_CPU_PLL);

		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;

		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;

		cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];

		break;

	default:

		cpu_clk = xtal_clk;

		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;

		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);

		xtal_mode = (syscfg >> 6) & 0x7;

		if (xtal_mode >= 6) {

			/* 25Mhz Xtal */

			cpu_clk = 25 * fbdiv * 1000 * 1000;

		} else if (xtal_mode >= 3) {

			/* 40Mhz Xtal */

			cpu_clk = 40 * fbdiv * 1000 * 1000;

		} else {

			/* 20Mhz Xtal */

			cpu_clk = 20 * fbdiv * 1000 * 1000;

		}



	cpu_clk = cpu_clk / ffiv * ffrac;

	bus_clk = cpu_clk / 4;



	clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);

	clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);



	pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);

	mips_hpt_frequency = cpu_clk / 2;

		break;

	}



static void __init mt7621_clocks_init_dt(struct device_node *np)

{

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

}



CLK_OF_DECLARE(mt7621_clk, "mediatek,mt7621-pll", mt7621_clocks_init_dt);



void __init ralink_of_remap(void)

{

	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");

arch/mips/ralink/timer-gic.c

+2 −2
Original line number Diff line number Diff line
@@ -11,14 +11,14 @@ 


#include <linux/of.h>

#include <linux/clk-provider.h>

#include <asm/time.h>

#include <linux/clocksource.h>



#include "common.h"



void __init plat_time_init(void)

{

	ralink_of_remap();

	ralink_clk_init();



	of_clk_init(NULL);

	timer_probe();

}