Commit 16921921 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rodrigo Vivi
Browse files

drm/i915/dsc: move rc_buf_thresh values to common helper 



The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagate them to
the drm_dsc_config.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230517102807.2181589-3-dmitry.baryshkov@linaro.org


Acked-by: default avatarDave Airlie <airlied@redhat.com>
parent a8c4b36e

drivers/gpu/drm/display/drm_dsc_helper.c

+35 −0
Original line number Diff line number Diff line
@@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, 
}

EXPORT_SYMBOL(drm_dsc_pps_payload_pack);



/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */

static const u16 drm_dsc_rc_buf_thresh[] = {

	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,

	7744, 7872, 8000, 8064

};



/**

 * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model

 * in accordance with the DSC 1.2 specification.

 *

 * @vdsc_cfg: DSC Configuration data partially filled by driver

 */

void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)

{

	int i;



	BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=

		     DSC_NUM_BUF_RANGES - 1);

	BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=

		     ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));



	for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)

		vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;



	/*

	 * For 6bpp, RC Buffer threshold 12 and 13 need a different value

	 * as per C Model

	 */

	if (vdsc_cfg->bits_per_pixel == 6 << 4) {

		vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;

		vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;

	}

}

EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);



/**

 * drm_dsc_compute_rc_parameters() - Write rate control

 * parameters to the dsc configuration defined in

drivers/gpu/drm/i915/display/intel_vdsc.c

+1 −23
Original line number Diff line number Diff line
@@ -37,12 +37,6 @@ enum COLUMN_INDEX_BPC { 
	MAX_COLUMN_INDEX

};



/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */

static const u16 rc_buf_thresh[] = {

	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,

	7744, 7872, 8000, 8064

};



struct rc_parameters {

	u16 initial_xmit_delay;

	u8 first_line_bpg_offset;
@@ -543,23 +537,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 


	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;



	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {

		/*

		 * six 0s are appended to the lsb of each threshold value

		 * internally in h/w.

		 * Only 8 bits are allowed for programming RcBufThreshold

		 */

		vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;

	}



	/*

	 * For 6bpp, RC Buffer threshold 12 and 13 need a different value

	 * as per C Model

	 */

	if (compressed_bpp == 6) {

		vdsc_cfg->rc_buf_thresh[12] = 0x7C;

		vdsc_cfg->rc_buf_thresh[13] = 0x7D;

	}

	drm_dsc_set_rc_buf_thresh(vdsc_cfg);



	/*

	 * From XE_LPD onwards we supports compression bpps in steps of 1

include/drm/display/drm_dsc_helper.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); 
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);

void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,

			      const struct drm_dsc_config *dsc_cfg);

void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);

int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);



#endif /* _DRM_DSC_HELPER_H_ */