Unverified Commit 16838bfb authored by Stefan Binding's avatar Stefan Binding Committed by Mark Brown
Browse files

ASoC: cs42l42: Wait for debounce interval after resume 



Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.

Signed-off-by: default avatarStefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-9-sbinding@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent e0bd53a4

sound/soc/codecs/cs42l42-sdw.c

+9 −1
Original line number Diff line number Diff line
@@ -447,7 +447,9 @@ static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs 


static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)

{

	static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500};

	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);

	unsigned int dbnce;

	int ret;



	dev_dbg(dev, "Runtime resume\n");
@@ -456,8 +458,14 @@ static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev) 
		return 0;



	ret = cs42l42_sdw_handle_unattach(cs42l42);

	if (ret < 0)

	if (ret < 0) {

		return ret;

	} else if (ret > 0) {

		dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall);



		if (dbnce > 0)

			msleep(ts_dbnce_ms[dbnce]);

	}



	regcache_cache_only(cs42l42->regmap, false);