Commit 1682bd1a authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Expand kernel doc for DC 



This commit adds extra documentation for elements related to FAMs.

Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Reviewed-by: default avatarAurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1a98cf8

drivers/gpu/drm/amd/display/dc/dc.h

+16 −3
Original line number Diff line number Diff line
@@ -494,9 +494,12 @@ enum dcn_zstate_support_state { 
	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,

	DCN_ZSTATE_SUPPORT_DISALLOW,

};

/*

 * For any clocks that may differ per pipe

 * only the max is stored in this structure



/**

 * dc_clocks - DC pipe clocks

 *

 * For any clocks that may differ per pipe only the max is stored in this

 * structure

 */

struct dc_clocks {

	int dispclk_khz;
@@ -523,6 +526,16 @@ struct dc_clocks { 
	bool prev_p_state_change_support;

	bool fclk_prev_p_state_change_support;

	int num_ways;



	/**

	 * @fw_based_mclk_switching

	 *

	 * DC has a mechanism that leverage the variable refresh rate to switch

	 * memory clock in cases that we have a large latency to achieve the

	 * memory clock change and a short vblank window. DC has some

	 * requirements to enable this feature, and this field describes if the

	 * system support or not such a feature.

	 */

	bool fw_based_mclk_switching;

	bool fw_based_mclk_switching_shut_down;

	int prev_num_ways;

drivers/gpu/drm/amd/display/dc/dc_stream.h

+11 −0
Original line number Diff line number Diff line
@@ -201,7 +201,18 @@ struct dc_stream_state { 
	bool use_vsc_sdp_for_colorimetry;

	bool ignore_msa_timing_param;



	/**

	 * @allow_freesync:

	 *

	 * It say if Freesync is enabled or not.

	 */

	bool allow_freesync;



	/**

	 * @vrr_active_variable:

	 *

	 * It describes if VRR is in use.

	 */

	bool vrr_active_variable;

	bool freesync_on_desktop;

drivers/gpu/drm/amd/display/dc/dml/dc_features.h

+7 −0
Original line number Diff line number Diff line
@@ -29,6 +29,13 @@ 
#define DC__PRESENT 1

#define DC__PRESENT__1 1

#define DC__NUM_DPP 4



/**

 * @DC__VOLTAGE_STATES:

 *

 * Define the maximum amount of states supported by the ASIC. Every ASIC has a

 * specific number of states; this macro defines the maximum number of states.

 */

#define DC__VOLTAGE_STATES 20

#define DC__NUM_DPP__4 1

#define DC__NUM_DPP__0_PRESENT 1

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

+25 −0
Original line number Diff line number Diff line
@@ -105,14 +105,39 @@ enum source_macro_tile_size { 
enum cursor_bpp {

	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2

};



/**

 * @enum clock_change_support - It represents possible reasons to change the DRAM clock.

 *

 * DC may change the DRAM clock during its execution, and this enum tracks all

 * the available methods. Note that every ASIC has their specific way to deal

 * with these clock switch.

 */

enum clock_change_support {

	/**

	 * @dm_dram_clock_change_uninitialized: If you see this, we might have

	 * a code initialization issue

	 */

	dm_dram_clock_change_uninitialized = 0,



	/**

	 * @dm_dram_clock_change_vactive: Support DRAM switch in VActive

	 */

	dm_dram_clock_change_vactive,



	/**

	 * @dm_dram_clock_change_vblank: Support DRAM switch in VBlank

	 */

	dm_dram_clock_change_vblank,



	dm_dram_clock_change_vactive_w_mall_full_frame,

	dm_dram_clock_change_vactive_w_mall_sub_vp,

	dm_dram_clock_change_vblank_w_mall_full_frame,

	dm_dram_clock_change_vblank_w_mall_sub_vp,



	/**

	 * @dm_dram_clock_change_unsupported: Do not support DRAM switch

	 */

	dm_dram_clock_change_unsupported

};

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

+9 −0
Original line number Diff line number Diff line
@@ -419,6 +419,15 @@ struct vba_vars_st { 
	double MinPixelChunkSizeBytes;

	unsigned int DCCMetaBufferSizeBytes;

	// Pipe/Plane Parameters



	/** @VoltageLevel:

	 * Every ASIC has a fixed number of DPM states, and some devices might

	 * have some particular voltage configuration that does not map

	 * directly to the DPM states. This field tells how many states the

	 * target device supports; even though this field combines the DPM and

	 * special SOC voltages, it mostly matches the total number of DPM

	 * states.

	 */

	int VoltageLevel;

	double FabricClock;

	double DRAMSpeed;