Commit 166ae731 authored by Jani Nikula's avatar Jani Nikula
Browse files

Merge tag 'gvt-fixes-2020-01-08' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2020-01-08

- Fix VFIO EDID on APL/BXT (Colin)

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210108045911.GF15982@zhen-hp.sh.intel.com
parents 2af52681 4ceb06e7

drivers/gpu/drm/i915/gvt/display.c

+57 −24
Original line number Diff line number Diff line
@@ -217,6 +217,15 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				  DDI_BUF_CTL_ENABLE);

			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

		}

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);

		/* No hpd_invert set in vgpu vbt, need to clear invert mask */

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;

		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;



		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
@@ -273,6 +282,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=

				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTA_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

		}
@@ -301,6 +312,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTB_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

		}
@@ -329,6 +342,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTC_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

		}
@@ -661,44 +676,62 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 
				PORTD_HOTPLUG_STATUS_MASK;

		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);

	} else if (IS_BROXTON(i915)) {

		if (connected) {

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

			} else {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

			}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTA_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTA_HOTPLUG_LONG_DETECT;

			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);

		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIB_DETECTED;

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

			}

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIC_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

			}

					SFUSE_STRAP_DDIB_DETECTED;

			} else {

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

			}

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

					~SFUSE_STRAP_DDIB_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

			}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTB_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTB_HOTPLUG_LONG_DETECT;

			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);

		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

					~SFUSE_STRAP_DDIC_DETECTED;

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIC_DETECTED;

			} else {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

					~SFUSE_STRAP_DDIC_DETECTED;

			}

		}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTC_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

			PORTB_HOTPLUG_STATUS_MASK;

		intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);

				PORTC_HOTPLUG_LONG_DETECT;

			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);

		}

	}

}

drivers/gpu/drm/i915/gvt/vgpu.c

+2 −3
Original line number Diff line number Diff line
@@ -437,10 +437,9 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 
	if (ret)

		goto out_clean_sched_policy;



	if (IS_BROADWELL(dev_priv))

	if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);

	/* FixMe: Re-enable APL/BXT once vfio_edid enabled */

	else if (!IS_BROXTON(dev_priv))

	else

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);

	if (ret)

		goto out_clean_sched_policy;