Commit 1660710c authored by Paul Cercueil's avatar Paul Cercueil Committed by Thomas Bogendoerfer
Browse files

MIPS: mm: XBurst CPU requires sync after DMA 



I am not sure why this is required, but if this is not enabled, reading
from a buffer in which data has been DMA'd may read incorrect values.

This used to happen for instance in mmc_app_send_scr()
(drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied
by the CPU to a different location.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent c8ba52d1

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ config MACH_INGENIC 
	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_ZBOOT

	select DMA_NONCOHERENT

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select IRQ_MIPS_CPU

	select PINCTRL

	select GPIOLIB

arch/mips/mm/dma-noncoherent.c

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void) 
	case CPU_R12000:

	case CPU_BMIPS5000:

	case CPU_LOONGSON2EF:

	case CPU_XBURST:

		return true;

	default:

		/*