Commit 16600343 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'phy-10g-mode-helper' 



Russell King says:

====================
Add phylink helper for 10G modes

During the last cycle, there was discussion about adding a helper
to set the 10G link modes for phylink, which resulted in these two
patches introduce such a helper.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 23b08260 14ad41c7

drivers/net/ethernet/cadence/macb_main.c

+1 −6
Original line number Diff line number Diff line
@@ -547,13 +547,8 @@ static void macb_validate(struct phylink_config *config, 
	if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&

	    (state->interface == PHY_INTERFACE_MODE_NA ||

	     state->interface == PHY_INTERFACE_MODE_10GBASER)) {

		phylink_set(mask, 10000baseCR_Full);

		phylink_set(mask, 10000baseER_Full);

		phylink_set_10g_modes(mask);

		phylink_set(mask, 10000baseKR_Full);

		phylink_set(mask, 10000baseLR_Full);

		phylink_set(mask, 10000baseLRM_Full);

		phylink_set(mask, 10000baseSR_Full);

		phylink_set(mask, 10000baseT_Full);

		if (state->interface != PHY_INTERFACE_MODE_NA)

			goto out;

	}

drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c

+1 −6
Original line number Diff line number Diff line
@@ -139,12 +139,7 @@ static void dpaa2_mac_validate(struct phylink_config *config, 
	case PHY_INTERFACE_MODE_NA:

	case PHY_INTERFACE_MODE_10GBASER:

	case PHY_INTERFACE_MODE_USXGMII:

		phylink_set(mask, 10000baseT_Full);

		phylink_set(mask, 10000baseCR_Full);

		phylink_set(mask, 10000baseSR_Full);

		phylink_set(mask, 10000baseLR_Full);

		phylink_set(mask, 10000baseLRM_Full);

		phylink_set(mask, 10000baseER_Full);

		phylink_set_10g_modes(mask);

		if (state->interface == PHY_INTERFACE_MODE_10GBASER)

			break;

		phylink_set(mask, 5000baseT_Full);

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+1 −6
Original line number Diff line number Diff line
@@ -6301,12 +6301,7 @@ static void mvpp2_phylink_validate(struct phylink_config *config, 
	case PHY_INTERFACE_MODE_XAUI:

	case PHY_INTERFACE_MODE_NA:

		if (mvpp2_port_supports_xlg(port)) {

			phylink_set(mask, 10000baseT_Full);

			phylink_set(mask, 10000baseCR_Full);

			phylink_set(mask, 10000baseSR_Full);

			phylink_set(mask, 10000baseLR_Full);

			phylink_set(mask, 10000baseLRM_Full);

			phylink_set(mask, 10000baseER_Full);

			phylink_set_10g_modes(mask);

			phylink_set(mask, 10000baseKR_Full);

		}

		if (state->interface != PHY_INTERFACE_MODE_NA)

drivers/net/phy/phylink.c

+11 −0
Original line number Diff line number Diff line
@@ -132,6 +132,17 @@ void phylink_set_port_modes(unsigned long *mask) 
}

EXPORT_SYMBOL_GPL(phylink_set_port_modes);



void phylink_set_10g_modes(unsigned long *mask)

{

	phylink_set(mask, 10000baseT_Full);

	phylink_set(mask, 10000baseCR_Full);

	phylink_set(mask, 10000baseSR_Full);

	phylink_set(mask, 10000baseLR_Full);

	phylink_set(mask, 10000baseLRM_Full);

	phylink_set(mask, 10000baseER_Full);

}

EXPORT_SYMBOL_GPL(phylink_set_10g_modes);



static int phylink_is_empty_linkmode(const unsigned long *linkmode)

{

	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp) = { 0, };

include/linux/phylink.h

+1 −0
Original line number Diff line number Diff line
@@ -484,6 +484,7 @@ int phylink_speed_up(struct phylink *pl); 
#define phylink_test(bm, mode)	__phylink_do_bit(test_bit, bm, mode)



void phylink_set_port_modes(unsigned long *bits);

void phylink_set_10g_modes(unsigned long *mask);

void phylink_helper_basex_speed(struct phylink_link_state *state);



void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,