Commit 163f4d22 authored by Sean Wang's avatar Sean Wang Committed by Felix Fietkau
Browse files

mt76: mt7921: add MAC support 



Add Rx packet description parsing, Tx packet description compositon, handle
packet recycling and provide MAC information mt76 core needs to support
mac80211.

Co-developed-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Co-developed-by: default avatarSoul Huang <Soul.Huang@mediatek.com>
Signed-off-by: default avatarSoul Huang <Soul.Huang@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 1755f6ad

drivers/net/wireless/mediatek/mt76/mt7921/mac.c

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File added.

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drivers/net/wireless/mediatek/mt76/mt7921/mac.h

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/* SPDX-License-Identifier: ISC */

/* Copyright (C) 2020 MediaTek Inc. */



#ifndef __MT7921_MAC_H

#define __MT7921_MAC_H



#define MT_CT_PARSE_LEN			72

#define MT_CT_DMA_BUF_NUM		2



#define MT_RXD0_LENGTH			GENMASK(15, 0)

#define MT_RXD0_PKT_FLAG                GENMASK(19, 16)

#define MT_RXD0_PKT_TYPE		GENMASK(31, 27)



#define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)

#define MT_RXD0_NORMAL_IP_SUM		BIT(23)

#define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)



enum rx_pkt_type {

	PKT_TYPE_TXS,

	PKT_TYPE_TXRXV,

	PKT_TYPE_NORMAL,

	PKT_TYPE_RX_DUP_RFB,

	PKT_TYPE_RX_TMR,

	PKT_TYPE_RETRIEVE,

	PKT_TYPE_TXRX_NOTIFY,

	PKT_TYPE_RX_EVENT,

	PKT_TYPE_NORMAL_MCU,

};



/* RXD DW1 */

#define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(9, 0)

#define MT_RXD1_NORMAL_GROUP_1		BIT(11)

#define MT_RXD1_NORMAL_GROUP_2		BIT(12)

#define MT_RXD1_NORMAL_GROUP_3		BIT(13)

#define MT_RXD1_NORMAL_GROUP_4		BIT(14)

#define MT_RXD1_NORMAL_GROUP_5		BIT(15)

#define MT_RXD1_NORMAL_SEC_MODE		GENMASK(20, 16)

#define MT_RXD1_NORMAL_KEY_ID		GENMASK(22, 21)

#define MT_RXD1_NORMAL_CM		BIT(23)

#define MT_RXD1_NORMAL_CLM		BIT(24)

#define MT_RXD1_NORMAL_ICV_ERR		BIT(25)

#define MT_RXD1_NORMAL_TKIP_MIC_ERR	BIT(26)

#define MT_RXD1_NORMAL_FCS_ERR		BIT(27)

#define MT_RXD1_NORMAL_BAND_IDX		BIT(28)

#define MT_RXD1_NORMAL_SPP_EN		BIT(29)

#define MT_RXD1_NORMAL_ADD_OM		BIT(30)

#define MT_RXD1_NORMAL_SEC_DONE		BIT(31)



/* RXD DW2 */

#define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)

#define MT_RXD2_NORMAL_CO_ANT		BIT(6)

#define MT_RXD2_NORMAL_BF_CQI		BIT(7)

#define MT_RXD2_NORMAL_MAC_HDR_LEN	GENMASK(12, 8)

#define MT_RXD2_NORMAL_HDR_TRANS	BIT(13)

#define MT_RXD2_NORMAL_HDR_OFFSET	GENMASK(15, 14)

#define MT_RXD2_NORMAL_TID		GENMASK(19, 16)

#define MT_RXD2_NORMAL_MU_BAR		BIT(21)

#define MT_RXD2_NORMAL_SW_BIT		BIT(22)

#define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)

#define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)

#define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)

#define MT_RXD2_NORMAL_INT_FRAME	BIT(26)

#define MT_RXD2_NORMAL_FRAG		BIT(27)

#define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)

#define MT_RXD2_NORMAL_NDATA		BIT(29)

#define MT_RXD2_NORMAL_NON_AMPDU	BIT(30)

#define MT_RXD2_NORMAL_BF_REPORT	BIT(31)



/* RXD DW3 */

#define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)

#define MT_RXD3_NORMAL_CH_FREQ		GENMASK(15, 8)

#define MT_RXD3_NORMAL_ADDR_TYPE	GENMASK(17, 16)

#define MT_RXD3_NORMAL_U2M		BIT(0)

#define MT_RXD3_NORMAL_HTC_VLD		BIT(0)

#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS	BIT(19)

#define MT_RXD3_NORMAL_BEACON_MC	BIT(20)

#define MT_RXD3_NORMAL_BEACON_UC	BIT(21)

#define MT_RXD3_NORMAL_AMSDU		BIT(22)

#define MT_RXD3_NORMAL_MESH		BIT(23)

#define MT_RXD3_NORMAL_MHCP		BIT(24)

#define MT_RXD3_NORMAL_NO_INFO_WB	BIT(25)

#define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS	BIT(26)

#define MT_RXD3_NORMAL_POWER_SAVE_STAT	BIT(27)

#define MT_RXD3_NORMAL_MORE		BIT(28)

#define MT_RXD3_NORMAL_UNWANT		BIT(29)

#define MT_RXD3_NORMAL_RX_DROP		BIT(30)

#define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)



/* RXD DW4 */

#define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)

#define MT_RXD4_NORMAL_PATTERN_DROP	BIT(9)

#define MT_RXD4_NORMAL_CLS		BIT(10)

#define MT_RXD4_NORMAL_OFLD		GENMASK(12, 11)

#define MT_RXD4_NORMAL_MAGIC_PKT	BIT(13)

#define MT_RXD4_NORMAL_WOL		GENMASK(18, 14)

#define MT_RXD4_NORMAL_CLS_BITMAP	GENMASK(28, 19)

#define MT_RXD3_NORMAL_PF_MODE		BIT(29)

#define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)



/* P-RXV */

#define MT_PRXV_TX_RATE			GENMASK(6, 0)

#define MT_PRXV_TX_DCM			BIT(4)

#define MT_PRXV_TX_ER_SU_106T		BIT(5)

#define MT_PRXV_NSTS			GENMASK(9, 7)

#define MT_PRXV_HT_AD_CODE		BIT(11)

#define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)

#define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)

#define MT_PRXV_RCPI3			GENMASK(31, 24)

#define MT_PRXV_RCPI2			GENMASK(23, 16)

#define MT_PRXV_RCPI1			GENMASK(15, 8)

#define MT_PRXV_RCPI0			GENMASK(7, 0)



/* C-RXV */

#define MT_CRXV_HT_STBC			GENMASK(1, 0)

#define MT_CRXV_TX_MODE			GENMASK(7, 4)

#define MT_CRXV_FRAME_MODE		GENMASK(10, 8)

#define MT_CRXV_HT_SHORT_GI		GENMASK(14, 13)

#define MT_CRXV_HE_LTF_SIZE		GENMASK(18, 17)

#define MT_CRXV_HE_LDPC_EXT_SYM		BIT(20)

#define MT_CRXV_HE_PE_DISAMBIG		BIT(23)

#define MT_CRXV_HE_UPLINK		BIT(31)



#define MT_CRXV_HE_SR_MASK		GENMASK(11, 8)

#define MT_CRXV_HE_SR1_MASK		GENMASK(16, 12)

#define MT_CRXV_HE_SR2_MASK             GENMASK(20, 17)

#define MT_CRXV_HE_SR3_MASK             GENMASK(24, 21)



#define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)

#define MT_CRXV_HE_TXOP_DUR		GENMASK(12, 6)

#define MT_CRXV_HE_BEAM_CHNG		BIT(13)

#define MT_CRXV_HE_DOPPLER		BIT(16)



#define MT_CRXV_SNR		GENMASK(18, 13)

#define MT_CRXV_FOE_LO		GENMASK(31, 19)

#define MT_CRXV_FOE_HI		GENMASK(6, 0)

#define MT_CRXV_FOE_SHIFT	13



enum tx_header_format {

	MT_HDR_FORMAT_802_3,

	MT_HDR_FORMAT_CMD,

	MT_HDR_FORMAT_802_11,

	MT_HDR_FORMAT_802_11_EXT,

};



enum tx_pkt_type {

	MT_TX_TYPE_CT,

	MT_TX_TYPE_SF,

	MT_TX_TYPE_CMD,

	MT_TX_TYPE_FW,

};



enum tx_port_idx {

	MT_TX_PORT_IDX_LMAC,

	MT_TX_PORT_IDX_MCU

};



enum tx_mcu_port_q_idx {

	MT_TX_MCU_PORT_RX_Q0 = 0x20,

	MT_TX_MCU_PORT_RX_Q1,

	MT_TX_MCU_PORT_RX_Q2,

	MT_TX_MCU_PORT_RX_Q3,

	MT_TX_MCU_PORT_RX_FWDL = 0x3e

};



#define MT_CT_INFO_APPLY_TXD		BIT(0)

#define MT_CT_INFO_COPY_HOST_TXD_ALL	BIT(1)

#define MT_CT_INFO_MGMT_FRAME		BIT(2)

#define MT_CT_INFO_NONE_CIPHER_FRAME	BIT(3)

#define MT_CT_INFO_HSR2_TX		BIT(4)

#define MT_CT_INFO_FROM_HOST		BIT(7)



#define MT_TXD_SIZE			(8 * 4)



#define MT_TXD0_Q_IDX			GENMASK(31, 25)

#define MT_TXD0_PKT_FMT			GENMASK(24, 23)

#define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)

#define MT_TXD0_TX_BYTES		GENMASK(15, 0)



#define MT_TXD1_LONG_FORMAT		BIT(31)

#define MT_TXD1_TGID			BIT(30)

#define MT_TXD1_OWN_MAC			GENMASK(29, 24)

#define MT_TXD1_AMSDU			BIT(23)

#define MT_TXD1_TID			GENMASK(22, 20)

#define MT_TXD1_HDR_PAD			GENMASK(19, 18)

#define MT_TXD1_HDR_FORMAT		GENMASK(17, 16)

#define MT_TXD1_HDR_INFO		GENMASK(15, 11)

#define MT_TXD1_ETH_802_3		BIT(15)

#define MT_TXD1_VTA			BIT(10)

#define MT_TXD1_WLAN_IDX		GENMASK(9, 0)



#define MT_TXD2_FIX_RATE		BIT(31)

#define MT_TXD2_FIXED_RATE		BIT(30)

#define MT_TXD2_POWER_OFFSET		GENMASK(29, 24)

#define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)

#define MT_TXD2_FRAG			GENMASK(15, 14)

#define MT_TXD2_HTC_VLD			BIT(13)

#define MT_TXD2_DURATION		BIT(12)

#define MT_TXD2_BIP			BIT(11)

#define MT_TXD2_MULTICAST		BIT(10)

#define MT_TXD2_RTS			BIT(9)

#define MT_TXD2_SOUNDING		BIT(8)

#define MT_TXD2_NDPA			BIT(7)

#define MT_TXD2_NDP			BIT(6)

#define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)

#define MT_TXD2_SUB_TYPE		GENMASK(3, 0)



#define MT_TXD3_SN_VALID		BIT(31)

#define MT_TXD3_PN_VALID		BIT(30)

#define MT_TXD3_SW_POWER_MGMT		BIT(29)

#define MT_TXD3_BA_DISABLE		BIT(28)

#define MT_TXD3_SEQ			GENMASK(27, 16)

#define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)

#define MT_TXD3_TX_COUNT		GENMASK(10, 6)

#define MT_TXD3_TIMING_MEASURE		BIT(5)

#define MT_TXD3_DAS			BIT(4)

#define MT_TXD3_EEOSP			BIT(3)

#define MT_TXD3_EMRD			BIT(2)

#define MT_TXD3_PROTECT_FRAME		BIT(1)

#define MT_TXD3_NO_ACK			BIT(0)



#define MT_TXD4_PN_LOW			GENMASK(31, 0)



#define MT_TXD5_PN_HIGH			GENMASK(31, 16)

#define MT_TXD5_MD			BIT(15)

#define MT_TXD5_ADD_BA			BIT(14)

#define MT_TXD5_TX_STATUS_HOST		BIT(10)

#define MT_TXD5_TX_STATUS_MCU		BIT(9)

#define MT_TXD5_TX_STATUS_FMT		BIT(8)

#define MT_TXD5_PID			GENMASK(7, 0)



#define MT_TXD6_TX_IBF			BIT(31)

#define MT_TXD6_TX_EBF			BIT(30)

#define MT_TXD6_TX_RATE			GENMASK(29, 16)

#define MT_TXD6_SGI			GENMASK(15, 14)

#define MT_TXD6_HELTF			GENMASK(13, 12)

#define MT_TXD6_LDPC			BIT(11)

#define MT_TXD6_SPE_ID_IDX		BIT(10)

#define MT_TXD6_ANT_ID			GENMASK(7, 4)

#define MT_TXD6_DYN_BW			BIT(3)

#define MT_TXD6_FIXED_BW		BIT(2)

#define MT_TXD6_BW			GENMASK(1, 0)



#define MT_TXD7_TXD_LEN			GENMASK(31, 30)

#define MT_TXD7_UDP_TCP_SUM		BIT(29)

#define MT_TXD7_IP_SUM			BIT(28)



#define MT_TXD7_TYPE			GENMASK(21, 20)

#define MT_TXD7_SUB_TYPE		GENMASK(19, 16)



#define MT_TXD7_PSE_FID			GENMASK(27, 16)

#define MT_TXD7_SPE_IDX			GENMASK(15, 11)

#define MT_TXD7_HW_AMSDU		BIT(10)

#define MT_TXD7_TX_TIME			GENMASK(9, 0)



#define MT_TX_RATE_STBC			BIT(13)

#define MT_TX_RATE_NSS			GENMASK(12, 10)

#define MT_TX_RATE_MODE			GENMASK(9, 6)

#define MT_TX_RATE_SU_EXT_TONE		BIT(5)

#define MT_TX_RATE_DCM			BIT(4)

#define MT_TX_RATE_IDX			GENMASK(3, 0)



#define MT_TXP_MAX_BUF_NUM		6



struct mt7921_txp {

	__le16 flags;

	__le16 token;

	u8 bss_idx;

	__le16 rept_wds_wcid;

	u8 nbuf;

	__le32 buf[MT_TXP_MAX_BUF_NUM];

	__le16 len[MT_TXP_MAX_BUF_NUM];

} __packed __aligned(4);



struct mt7921_tx_free {

	__le16 rx_byte_cnt;

	__le16 ctrl;

	u8 txd_cnt;

	u8 rsv[3];

	__le32 info[];

} __packed __aligned(4);



#define MT_TX_FREE_MSDU_CNT		GENMASK(9, 0)

#define MT_TX_FREE_WLAN_ID		GENMASK(23, 14)

#define MT_TX_FREE_LATENCY		GENMASK(12, 0)

/* 0: success, others: dropped */

#define MT_TX_FREE_STATUS		GENMASK(14, 13)

#define MT_TX_FREE_MSDU_ID		GENMASK(30, 16)

#define MT_TX_FREE_PAIR			BIT(31)

/* will support this field in further revision */

#define MT_TX_FREE_RATE			GENMASK(13, 0)



static inline struct mt7921_txp_common *

mt7921_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)

{

	u8 *txwi;



	if (!t)

		return NULL;



	txwi = mt76_get_txwi_ptr(dev, t);



	return (struct mt7921_txp_common *)(txwi + MT_TXD_SIZE);

}



#define MT_HW_TXP_MAX_MSDU_NUM		4

#define MT_HW_TXP_MAX_BUF_NUM		4



#define MT_MSDU_ID_VALID		BIT(15)



#define MT_TXD_LEN_MASK			GENMASK(11, 0)

#define MT_TXD_LEN_MSDU_LAST		BIT(14)

#define MT_TXD_LEN_AMSDU_LAST		BIT(15)

#define MT_TXD_LEN_LAST			BIT(15)



struct mt7921_txp_ptr {

	__le32 buf0;

	__le16 len0;

	__le16 len1;

	__le32 buf1;

} __packed __aligned(4);



struct mt7921_hw_txp {

	__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];

	struct mt7921_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];

} __packed __aligned(4);



struct mt7921_txp_common {

	union {

		struct mt7921_hw_txp hw;

	};

};



#endif

drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h

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/* SPDX-License-Identifier: ISC */

/* Copyright (C) 2020 MediaTek Inc. */



#ifndef __MT7921_H

#define __MT7921_H



#include <linux/interrupt.h>

#include <linux/ktime.h>

#include "../mt76.h"

#include "regs.h"



#define MT7921_MAX_INTERFACES		4

#define MT7921_MAX_WMM_SETS		4

#define MT7921_WTBL_SIZE		20

#define MT7921_WTBL_RESERVED		(MT7921_WTBL_SIZE - 1)

#define MT7921_WTBL_STA			(MT7921_WTBL_RESERVED - \

					 MT7921_MAX_INTERFACES)



#define MT7921_HW_SCAN_TIMEOUT		(HZ / 10)

#define MT7921_WATCHDOG_TIME		(HZ / 10)

#define MT7921_RESET_TIMEOUT		(30 * HZ)



#define MT7921_TX_RING_SIZE		2048

#define MT7921_TX_MCU_RING_SIZE		256

#define MT7921_TX_FWDL_RING_SIZE	128



#define MT7921_RX_RING_SIZE		1536

#define MT7921_RX_MCU_RING_SIZE		512



#define MT7921_FIRMWARE_WM		"mediatek/WIFI_RAM_CODE_MT7961_1.bin"

#define MT7921_ROM_PATCH		"mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin"



#define MT7921_EEPROM_SIZE		3584

#define MT7921_TOKEN_SIZE		8192

#define MT7921_TOKEN_FREE_THR		64



#define MT7921_CFEND_RATE_DEFAULT	0x49	/* OFDM 24M */

#define MT7921_CFEND_RATE_11B		0x03	/* 11B LP, 11M */

#define MT7921_5G_RATE_DEFAULT		0x4b	/* OFDM 6M */

#define MT7921_2G_RATE_DEFAULT		0x0	/* CCK 1M */



#define MT7921_SKU_RATE_NUM		161

#define MT7921_SKU_MAX_DELTA_IDX	MT7921_SKU_RATE_NUM

#define MT7921_SKU_TABLE_SIZE		(MT7921_SKU_RATE_NUM + 1)



#define MT7921_SCAN_IE_LEN		600



struct mt7921_vif;

struct mt7921_sta;



enum mt7921_txq_id {

	MT7921_TXQ_BAND0,

	MT7921_TXQ_BAND1,

	MT7921_TXQ_FWDL = 16,

	MT7921_TXQ_MCU_WM,

};



enum mt7921_rxq_id {

	MT7921_RXQ_BAND0 = 0,

	MT7921_RXQ_BAND1,

	MT7921_RXQ_MCU_WM = 0,

};



struct mt7921_sta_stats {

	struct rate_info prob_rate;

	struct rate_info tx_rate;



	unsigned long per;

	unsigned long changed;

	unsigned long jiffies;

};



struct mt7921_sta_key_conf {

	s8 keyidx;

	u8 key[16];

};



struct mt7921_sta {

	struct mt76_wcid wcid; /* must be first */



	struct mt7921_vif *vif;



	struct list_head stats_list;

	struct list_head poll_list;

	u32 airtime_ac[8];



	struct mt7921_sta_stats stats;



	unsigned long ampdu_state;



	struct mt7921_sta_key_conf bip;

};



struct mt7921_vif {

	struct mt76_vif mt76; /* must be first */



	struct mt7921_sta sta;

	struct mt7921_phy *phy;



	struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];

};



struct mib_stats {

	u16 ack_fail_cnt;

	u16 fcs_err_cnt;

	u16 rts_cnt;

	u16 rts_retries_cnt;

	u16 ba_miss_cnt;

};



struct mt7921_phy {

	struct mt76_phy *mt76;

	struct mt7921_dev *dev;



	struct ieee80211_sband_iftype_data iftype[2][NUM_NL80211_IFTYPES];



	struct ieee80211_vif *monitor_vif;



	u32 rxfilter;

	u64 omac_mask;



	u16 noise;



	s16 coverage_class;

	u8 slottime;



	__le32 rx_ampdu_ts;

	u32 ampdu_ref;



	struct mib_stats mib;

	struct list_head stats_list;



	struct sk_buff_head scan_event_list;

	struct delayed_work scan_work;

};



struct mt7921_dev {

	union { /* must be first */

		struct mt76_dev mt76;

		struct mt76_phy mphy;

	};



	const struct mt76_bus_ops *bus_ops;

	struct mt7921_phy phy;

	struct tasklet_struct irq_tasklet;



	u16 chainmask;



	struct work_struct init_work;

	struct work_struct reset_work;

	wait_queue_head_t reset_wait;

	u32 reset_state;



	struct list_head sta_poll_list;

	spinlock_t sta_poll_lock;



	spinlock_t token_lock;

	int token_count;

	struct idr token;



	u8 fw_debug;

};



enum {

	HW_BSSID_0 = 0x0,

	HW_BSSID_1,

	HW_BSSID_2,

	HW_BSSID_3,

	HW_BSSID_MAX = HW_BSSID_3,

	EXT_BSSID_START = 0x10,

	EXT_BSSID_1,

	EXT_BSSID_15 = 0x1f,

	EXT_BSSID_MAX = EXT_BSSID_15,

	REPEATER_BSSID_START = 0x20,

	REPEATER_BSSID_MAX = 0x3f,

};



enum {

	MT_LMAC_AC00,

	MT_LMAC_AC01,

	MT_LMAC_AC02,

	MT_LMAC_AC03,

	MT_LMAC_ALTX0 = 0x10,

	MT_LMAC_BMC0,

	MT_LMAC_BCN0,

};



static inline struct mt7921_phy *

mt7921_hw_phy(struct ieee80211_hw *hw)

{

	struct mt76_phy *phy = hw->priv;



	return phy->priv;

}



static inline struct mt7921_dev *

mt7921_hw_dev(struct ieee80211_hw *hw)

{

	struct mt76_phy *phy = hw->priv;



	return container_of(phy->dev, struct mt7921_dev, mt76);

}



static inline u8 mt7921_lmac_mapping(struct mt7921_dev *dev, u8 ac)

{

	/* LMAC uses the reverse order of mac80211 AC indexes */

	return 3 - ac;

}



extern const struct ieee80211_ops mt7921_ops;

extern struct pci_driver mt7921_pci_driver;



u32 mt7921_reg_map(struct mt7921_dev *dev, u32 addr);



int mt7921_register_device(struct mt7921_dev *dev);

void mt7921_unregister_device(struct mt7921_dev *dev);

int mt7921_eeprom_init(struct mt7921_dev *dev);

void mt7921_eeprom_parse_band_config(struct mt7921_phy *phy);

int mt7921_eeprom_get_target_power(struct mt7921_dev *dev,

				   struct ieee80211_channel *chan,

				   u8 chain_idx);

void mt7921_eeprom_init_sku(struct mt7921_dev *dev);

int mt7921_dma_init(struct mt7921_dev *dev);

void mt7921_dma_prefetch(struct mt7921_dev *dev);

void mt7921_dma_cleanup(struct mt7921_dev *dev);

int mt7921_mcu_init(struct mt7921_dev *dev);

int mt7921_mcu_add_bss_info(struct mt7921_phy *phy,

			    struct ieee80211_vif *vif, int enable);

int mt7921_mcu_add_key(struct mt7921_dev *dev, struct ieee80211_vif *vif,

		       struct mt7921_sta *msta, struct ieee80211_key_conf *key,

		       enum set_key_cmd cmd);

int mt7921_set_channel(struct mt7921_phy *phy);

int mt7921_mcu_set_chan_info(struct mt7921_phy *phy, int cmd);

int mt7921_mcu_set_tx(struct mt7921_dev *dev, struct ieee80211_vif *vif);

int mt7921_mcu_set_eeprom(struct mt7921_dev *dev);

int mt7921_mcu_get_eeprom(struct mt7921_dev *dev, u32 offset);

int mt7921_mcu_set_mac(struct mt7921_dev *dev, int band, bool enable,

		       bool hdr_trans);

int mt7921_mcu_set_rts_thresh(struct mt7921_phy *phy, u32 val);

int mt7921_mcu_fw_log_2_host(struct mt7921_dev *dev, u8 ctrl);

void mt7921_mcu_rx_event(struct mt7921_dev *dev, struct sk_buff *skb);

void mt7921_mcu_exit(struct mt7921_dev *dev);



static inline bool is_mt7921(struct mt76_dev *dev)

{

	return mt76_chip(dev) == 0x7961;

}



static inline void mt7921_irq_enable(struct mt7921_dev *dev, u32 mask)

{

	mt76_set_irq_mask(&dev->mt76, 0, 0, mask);



	tasklet_schedule(&dev->irq_tasklet);

}



static inline u32

mt7921_reg_map_l1(struct mt7921_dev *dev, u32 addr)

{

	u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);

	u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);



	mt76_rmw_field(dev, MT_HIF_REMAP_L1, MT_HIF_REMAP_L1_MASK, base);

	/* use read to push write */

	mt76_rr(dev, MT_HIF_REMAP_L1);



	return MT_HIF_REMAP_BASE_L1 + offset;

}



static inline u32

mt7921_l1_rr(struct mt7921_dev *dev, u32 addr)

{

	return mt76_rr(dev, mt7921_reg_map_l1(dev, addr));

}



static inline void

mt7921_l1_wr(struct mt7921_dev *dev, u32 addr, u32 val)

{

	mt76_wr(dev, mt7921_reg_map_l1(dev, addr), val);

}



static inline u32

mt7921_l1_rmw(struct mt7921_dev *dev, u32 addr, u32 mask, u32 val)

{

	val |= mt7921_l1_rr(dev, addr) & ~mask;

	mt7921_l1_wr(dev, addr, val);



	return val;

}



#define mt7921_l1_set(dev, addr, val)	mt7921_l1_rmw(dev, addr, 0, val)

#define mt7921_l1_clear(dev, addr, val)	mt7921_l1_rmw(dev, addr, val, 0)



bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask);

void mt7921_mac_reset_counters(struct mt7921_phy *phy);

void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi,

			   struct sk_buff *skb, struct mt76_wcid *wcid,

			   struct ieee80211_key_conf *key, bool beacon);

void mt7921_mac_set_timing(struct mt7921_phy *phy);

int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb);

void mt7921_mac_fill_rx_vector(struct mt7921_dev *dev, struct sk_buff *skb);

void mt7921_mac_tx_free(struct mt7921_dev *dev, struct sk_buff *skb);

int mt7921_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,

		       struct ieee80211_sta *sta);

void mt7921_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,

			   struct ieee80211_sta *sta);

void mt7921_mac_work(struct work_struct *work);

void mt7921_mac_reset_work(struct work_struct *work);

int mt7921_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,

			  enum mt76_txq_id qid, struct mt76_wcid *wcid,

			  struct ieee80211_sta *sta,

			  struct mt76_tx_info *tx_info);

void mt7921_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);

int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc);

void mt7921_tx_token_put(struct mt7921_dev *dev);

void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,

			 struct sk_buff *skb);

void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);

void mt7921_stats_work(struct work_struct *work);

void mt7921_txp_skb_unmap(struct mt76_dev *dev,

			  struct mt76_txwi_cache *txwi);

void mt7921_set_stream_he_caps(struct mt7921_phy *phy);

void mt7921_update_channel(struct mt76_dev *mdev);

int mt7921_init_debugfs(struct mt7921_dev *dev);

int

mt7921_mcu_uni_add_dev(struct mt7921_dev *dev,

		       struct ieee80211_vif *vif, bool enable);

int

mt7921_mcu_uni_add_bss(struct mt7921_phy *phy, struct ieee80211_vif *vif,

		       bool enable);



int

mt7921_mcu_uni_add_sta(struct mt7921_dev *dev, struct ieee80211_vif *vif,

		       struct ieee80211_sta *sta, bool enable);

int mt7921_mcu_uni_tx_ba(struct mt7921_dev *dev,

			 struct ieee80211_ampdu_params *params,

			 bool enable);

int mt7921_mcu_uni_rx_ba(struct mt7921_dev *dev,

			 struct ieee80211_ampdu_params *params,

			 bool enable);

void mt7921_scan_work(struct work_struct *work);

int mt7921_mcu_set_channel_domain(struct mt7921_phy *phy);

int mt7921_mcu_hw_scan(struct mt7921_phy *phy, struct ieee80211_vif *vif,

		       struct ieee80211_scan_request *scan_req);

int mt7921_mcu_cancel_hw_scan(struct mt7921_phy *phy,

			      struct ieee80211_vif *vif);

u32 mt7921_get_wtbl_info(struct mt7921_dev *dev, u16 wlan_idx);

#endif

drivers/net/wireless/mediatek/mt76/mt7921/regs.h

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