Commit 163d3f80 authored by Fuad Tabba's avatar Fuad Tabba Committed by Will Deacon
Browse files

arm64: dcache_by_line_op to take end parameter instead of size 



To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: default avatarWill Deacon <will@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-12-tabba@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent e3974adb

arch/arm64/include/asm/assembler.h

+13 −14
Original line number Diff line number Diff line
@@ -397,40 +397,39 @@ alternative_endif 


/*

 * Macro to perform a data cache maintenance for the interval

 * [addr, addr + size)

 * [start, end)

 *

 * 	op:		operation passed to dc instruction

 * 	domain:		domain used in dsb instruciton

 * 	addr:		starting virtual address of the region

 * 	size:		size of the region

 * 	start:          starting virtual address of the region

 * 	end:            end virtual address of the region

 * 	fixup:		optional label to branch to on user fault

 * 	Corrupts:	addr, size, tmp1, tmp2

 * 	Corrupts:       start, end, tmp1, tmp2

 */

	.macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2, fixup

	.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup

	dcache_line_size \tmp1, \tmp2

	add	\size, \addr, \size

	sub	\tmp2, \tmp1, #1

	bic	\addr, \addr, \tmp2

	bic	\start, \start, \tmp2

.Ldcache_op\@:

	.ifc	\op, cvau

	__dcache_op_workaround_clean_cache \op, \addr

	__dcache_op_workaround_clean_cache \op, \start

	.else

	.ifc	\op, cvac

	__dcache_op_workaround_clean_cache \op, \addr

	__dcache_op_workaround_clean_cache \op, \start

	.else

	.ifc	\op, cvap

	sys	3, c7, c12, 1, \addr	// dc cvap

	sys	3, c7, c12, 1, \start	// dc cvap

	.else

	.ifc	\op, cvadp

	sys	3, c7, c13, 1, \addr	// dc cvadp

	sys	3, c7, c13, 1, \start	// dc cvadp

	.else

	dc	\op, \addr

	dc	\op, \start

	.endif

	.endif

	.endif

	.endif

	add	\addr, \addr, \tmp1

	cmp	\addr, \size

	add	\start, \start, \tmp1

	cmp	\start, \end

	b.lo	.Ldcache_op\@

	dsb	\domain

arch/arm64/kvm/hyp/nvhe/cache.S

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <asm/alternative.h>



SYM_FUNC_START_PI(__flush_dcache_area)

	add	x1, x0, x1

	dcache_by_line_op civac, sy, x0, x1, x2, x3

	ret

SYM_FUNC_END_PI(__flush_dcache_area)

arch/arm64/mm/cache.S

+6 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ alternative_if ARM64_HAS_CACHE_IDC 
	b       .Ldc_skip_\@

alternative_else_nop_endif

	mov     x2, x0

	sub     x3, x1, x0

	mov     x3, x1

	dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup

.Ldc_skip_\@:

alternative_if ARM64_HAS_CACHE_DIC
@@ -108,6 +108,7 @@ SYM_FUNC_END(invalidate_icache_range) 
 *	- size    - size in question

 */

SYM_FUNC_START_PI(__flush_dcache_area)

	add	x1, x0, x1

	dcache_by_line_op civac, sy, x0, x1, x2, x3

	ret

SYM_FUNC_END_PI(__flush_dcache_area)
@@ -126,6 +127,7 @@ alternative_if ARM64_HAS_CACHE_IDC 
	dsb	ishst

	ret

alternative_else_nop_endif

	add	x1, x0, x1

	dcache_by_line_op cvau, ish, x0, x1, x2, x3

	ret

SYM_FUNC_END(__clean_dcache_area_pou)
@@ -187,6 +189,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_poc) 
 *	- start   - virtual start address of region

 *	- size    - size in question

 */

	add	x1, x0, x1

	dcache_by_line_op cvac, sy, x0, x1, x2, x3

	ret

SYM_FUNC_END_PI(__clean_dcache_area_poc)
@@ -205,6 +208,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_pop) 
	alternative_if_not ARM64_HAS_DCPOP

	b	__clean_dcache_area_poc

	alternative_else_nop_endif

	add	x1, x0, x1

	dcache_by_line_op cvap, sy, x0, x1, x2, x3

	ret

SYM_FUNC_END_PI(__clean_dcache_area_pop)
@@ -218,6 +222,7 @@ SYM_FUNC_END_PI(__clean_dcache_area_pop) 
 *	- size    - size in question

 */

SYM_FUNC_START_PI(__dma_flush_area)

	add	x1, x0, x1

	dcache_by_line_op civac, sy, x0, x1, x2, x3

	ret

SYM_FUNC_END_PI(__dma_flush_area)