Commit 1625fbc1 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Support sd clk mux round operation 



Currently, determine_rate() is not doing any round operation
and due to this it always selects a lower clock source compared
to the closest higher one.

Support sd clk mux round operation by passing
CLK_MUX_ROUND_CLOSEST flag to clk_mux_determine_rate_flags().

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220919084110.3065156-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 9abf2313

drivers/clk/renesas/rzg2l-cpg.c

+1 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, 
static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw,

					       struct clk_rate_request *req)

{

	return clk_mux_determine_rate_flags(hw, req, 0);

	return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);

}



static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)