Unverified Commit 16252e01 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe" 

Evan Green <evan@rivosinc.com> says:

This change detects the presence of Zba, Zbb, and Zbs extensions and exports
them per-hart to userspace via the hwprobe mechanism. Glibc can then use
these in setting up hwcaps-based library search paths.

There's a little bit of extra housekeeping here: the first change adds
Zba and Zbs to the set of extensions the kernel recognizes, and the second
change starts tracking ISA features per-hart (in addition to the ANDed
mask of features across all harts which the kernel uses to make
decisions). Now that we track the ISA information per-hart, we could
even fix up /proc/cpuinfo to accurately report extension per-hart,
though I've left that out of this series for now.

* b4-shazam-merge:
  RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
  RISC-V: Track ISA extensions per hart
  RISC-V: Add Zba, Zbs extension probing

Link: https://lore.kernel.org/r/20230509182504.2997252-1-evan@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents f2023385 c0baf321

Documentation/riscv/hwprobe.rst

+10 −0
Original line number Diff line number Diff line
@@ -67,6 +67,16 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by

    version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is

       supported, as defined in version 1.0 of the Bit-Manipulation ISA

       extensions.



  * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined

       in version 1.0 of the Bit-Manipulation ISA extensions.



  * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined

       in version 1.0 of the Bit-Manipulation ISA extensions.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/asm/cpufeature.h

+10 −0
Original line number Diff line number Diff line
@@ -6,6 +6,9 @@ 
#ifndef _ASM_CPUFEATURE_H

#define _ASM_CPUFEATURE_H



#include <linux/bitmap.h>

#include <asm/hwcap.h>



/*

 * These are probed via a device_initcall(), via either the SBI or directly

 * from the corresponding CSRs.
@@ -16,8 +19,15 @@ struct riscv_cpuinfo { 
	unsigned long mimpid;

};



struct riscv_isainfo {

	DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);

};



DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);



DECLARE_PER_CPU(long, misaligned_access_speed);



/* Per-cpu ISA extensions. */

extern struct riscv_isainfo hart_isa[NR_CPUS];



#endif

arch/riscv/include/asm/hwcap.h

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ 
#define RISCV_ISA_EXT_ZICBOZ		34

#define RISCV_ISA_EXT_SMAIA		35

#define RISCV_ISA_EXT_SSAIA		36

#define RISCV_ISA_EXT_ZBA		37

#define RISCV_ISA_EXT_ZBS		38



#define RISCV_ISA_EXT_MAX		64

#define RISCV_ISA_EXT_NAME_LEN_MAX	32

arch/riscv/include/uapi/asm/hwprobe.h

+3 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_IMA_FD		(1 << 0)

#define		RISCV_HWPROBE_IMA_C		(1 << 1)

#define		RISCV_HWPROBE_IMA_V		(1 << 2)

#define		RISCV_HWPROBE_EXT_ZBA		(1 << 3)

#define		RISCV_HWPROBE_EXT_ZBB		(1 << 4)

#define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/cpu.c

+2 −0
Original line number Diff line number Diff line
@@ -187,7 +187,9 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { 
	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),

	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),

	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),

	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),

	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),