Commit 16178c8e authored by Piergiorgio Beruto's avatar Piergiorgio Beruto Committed by David S. Miller
Browse files

drivers/net/phy: add the link modes for the 10BASE-T1S Ethernet PHY 



This patch adds the link modes for the IEEE 802.3cg Clause 147 10BASE-T1S
Ethernet PHY. According to the specifications, the 10BASE-T1S supports
Point-To-Point Full-Duplex, Point-To-Point Half-Duplex and/or
Point-To-Multipoint (AKA Multi-Drop) Half-Duplex operations.

Signed-off-by: default avatarPiergiorgio Beruto <piergiorgio.beruto@gmail.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8580e16c

drivers/net/phy/phy-core.c

+4 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 */

const char *phy_speed_to_str(int speed)

{

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102,

		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "

		"If a speed or mode has been added please update phy_speed_to_str "

		"and the PHY settings array.\n");
@@ -260,6 +260,9 @@ static const struct phy_setting settings[] = { 
	PHY_SETTING(     10, FULL,     10baseT_Full		),

	PHY_SETTING(     10, HALF,     10baseT_Half		),

	PHY_SETTING(     10, FULL,     10baseT1L_Full		),

	PHY_SETTING(     10, FULL,     10baseT1S_Full		),

	PHY_SETTING(     10, HALF,     10baseT1S_Half		),

	PHY_SETTING(     10, HALF,     10baseT1S_P2MP_Half	),

};

#undef PHY_SETTING

drivers/net/phy/phy_device.c

+14 −0
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ EXPORT_SYMBOL_GPL(phy_basic_features); 
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;

EXPORT_SYMBOL_GPL(phy_basic_t1_features);



__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;

EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features);



__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;

EXPORT_SYMBOL_GPL(phy_gbit_features);
@@ -98,6 +101,12 @@ const int phy_basic_t1_features_array[3] = { 
};

EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);



const int phy_basic_t1s_p2mp_features_array[2] = {

	ETHTOOL_LINK_MODE_TP_BIT,

	ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT,

};

EXPORT_SYMBOL_GPL(phy_basic_t1s_p2mp_features_array);



const int phy_gbit_features_array[2] = {

	ETHTOOL_LINK_MODE_1000baseT_Half_BIT,

	ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
@@ -138,6 +147,11 @@ static void features_init(void) 
			       ARRAY_SIZE(phy_basic_t1_features_array),

			       phy_basic_t1_features);



	/* 10 half, P2MP, TP */

	linkmode_set_bit_array(phy_basic_t1s_p2mp_features_array,

			       ARRAY_SIZE(phy_basic_t1s_p2mp_features_array),

			       phy_basic_t1s_p2mp_features);



	/* 10/100 half/full + 1000 half/full */

	linkmode_set_bit_array(phy_basic_ports_array,

			       ARRAY_SIZE(phy_basic_ports_array),

drivers/net/phy/phylink.c

+5 −1
Original line number Diff line number Diff line
@@ -241,12 +241,16 @@ void phylink_caps_to_linkmodes(unsigned long *linkmodes, unsigned long caps) 
	if (caps & MAC_ASYM_PAUSE)

		__set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, linkmodes);



	if (caps & MAC_10HD)

	if (caps & MAC_10HD) {

		__set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes);

		__set_bit(ETHTOOL_LINK_MODE_10baseT1S_Half_BIT, linkmodes);

		__set_bit(ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT, linkmodes);

	}



	if (caps & MAC_10FD) {

		__set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes);

		__set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, linkmodes);

		__set_bit(ETHTOOL_LINK_MODE_10baseT1S_Full_BIT, linkmodes);

	}



	if (caps & MAC_100HD) {

include/linux/phy.h

+14 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 


extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
@@ -54,6 +55,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_ini 


#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)

#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)

#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)

#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)

#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)

#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
@@ -66,6 +68,7 @@ extern const int phy_fibre_port_array[1]; 
extern const int phy_all_ports_features_array[7];

extern const int phy_10_100_features_array[4];

extern const int phy_basic_t1_features_array[3];

extern const int phy_basic_t1s_p2mp_features_array[2];

extern const int phy_gbit_features_array[2];

extern const int phy_10gbit_features_array[1];
@@ -1041,6 +1044,17 @@ struct phy_driver { 
	int (*get_sqi)(struct phy_device *dev);

	/** @get_sqi_max: Get the maximum signal quality indication */

	int (*get_sqi_max)(struct phy_device *dev);



	/* PLCA RS interface */

	/** @get_plca_cfg: Return the current PLCA configuration */

	int (*get_plca_cfg)(struct phy_device *dev,

			    struct phy_plca_cfg *plca_cfg);

	/** @set_plca_cfg: Set the PLCA configuration */

	int (*set_plca_cfg)(struct phy_device *dev,

			    const struct phy_plca_cfg *plca_cfg);

	/** @get_plca_status: Return the current PLCA status info */

	int (*get_plca_status)(struct phy_device *dev,

			       struct phy_plca_status *plca_st);

};

#define to_phy_driver(d) container_of(to_mdio_common_driver(d),		\

				      struct phy_driver, mdiodrv)

include/uapi/linux/ethtool.h

+3 −0
Original line number Diff line number Diff line
@@ -1741,6 +1741,9 @@ enum ethtool_link_mode_bit_indices { 
	ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT	 = 96,

	ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT	 = 97,

	ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT	 = 98,

	ETHTOOL_LINK_MODE_10baseT1S_Full_BIT		 = 99,

	ETHTOOL_LINK_MODE_10baseT1S_Half_BIT		 = 100,

	ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT	 = 101,



	/* must be last entry */

	__ETHTOOL_LINK_MODE_MASK_NBITS