Commit 1606e815 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() 



Fix clock index out of range check for module clocks in
rzg2l_cpg_clk_src_twocell_get().

Fixes: ef3c613c ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e37868f1

drivers/clk/renesas/renesas-rzg2l-cpg.c

+1 −1
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ static struct clk 


	case CPG_MOD:

		type = "module";

		if (clkidx > priv->num_mod_clks) {

		if (clkidx >= priv->num_mod_clks) {

			dev_err(dev, "Invalid %s clock index %u\n", type,

				clkidx);

			return ERR_PTR(-EINVAL);