Commit 15fa3e8e authored by Matthew Wilcox (Oracle)'s avatar Matthew Wilcox (Oracle) Committed by Andrew Morton
Browse files

mips: implement the new page table range API 

Rename _PFN_SHIFT to PFN_PTE_SHIFT.  Convert a few places
to call set_pte() instead of set_pte_at().  Add set_ptes(),
update_mmu_cache_range(), flush_icache_pages() and flush_dcache_folio().
Change the PG_arch_1 (aka PG_dcache_dirty) flag from being per-page
to per-folio.

Link: https://lkml.kernel.org/r/20230802151406.3735276-18-willy@infradead.org


Signed-off-by: default avatarMatthew Wilcox (Oracle) <willy@infradead.org>
Acked-by: default avatarMike Rapoport (IBM) <rppt@kernel.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent 27a8b944

arch/mips/bcm47xx/prom.c

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ void __init prom_init(void) 
#if defined(CONFIG_BCM47XX_BCMA) && defined(CONFIG_HIGHMEM)



#define EXTVBASE	0xc0000000

#define ENTRYLO(x)	((pte_val(pfn_pte((x) >> _PFN_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6) | 1)

#define ENTRYLO(x)	((pte_val(pfn_pte((x) >> PFN_PTE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6) | 1)



#include <asm/tlbflush.h>

arch/mips/include/asm/cacheflush.h

+21 −11
Original line number Diff line number Diff line
@@ -36,12 +36,12 @@ 
 */

#define PG_dcache_dirty			PG_arch_1



#define Page_dcache_dirty(page)		\

	test_bit(PG_dcache_dirty, &(page)->flags)

#define SetPageDcacheDirty(page)	\

	set_bit(PG_dcache_dirty, &(page)->flags)

#define ClearPageDcacheDirty(page)	\

	clear_bit(PG_dcache_dirty, &(page)->flags)

#define folio_test_dcache_dirty(folio)		\

	test_bit(PG_dcache_dirty, &(folio)->flags)

#define folio_set_dcache_dirty(folio)	\

	set_bit(PG_dcache_dirty, &(folio)->flags)

#define folio_clear_dcache_dirty(folio)	\

	clear_bit(PG_dcache_dirty, &(folio)->flags)



extern void (*flush_cache_all)(void);

extern void (*__flush_cache_all)(void);
@@ -50,15 +50,24 @@ extern void (*flush_cache_mm)(struct mm_struct *mm); 
extern void (*flush_cache_range)(struct vm_area_struct *vma,

	unsigned long start, unsigned long end);

extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);

extern void __flush_dcache_page(struct page *page);

extern void __flush_dcache_pages(struct page *page, unsigned int nr);



#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1

static inline void flush_dcache_folio(struct folio *folio)

{

	if (cpu_has_dc_aliases)

		__flush_dcache_pages(&folio->page, folio_nr_pages(folio));

	else if (!cpu_has_ic_fills_f_dc)

		folio_set_dcache_dirty(folio);

}

#define flush_dcache_folio flush_dcache_folio



static inline void flush_dcache_page(struct page *page)

{

	if (cpu_has_dc_aliases)

		__flush_dcache_page(page);

		__flush_dcache_pages(page, 1);

	else if (!cpu_has_ic_fills_f_dc)

		SetPageDcacheDirty(page);

		folio_set_dcache_dirty(page_folio(page));

}



#define flush_dcache_mmap_lock(mapping)		do { } while (0)
@@ -73,10 +82,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma, 
		__flush_anon_page(page, vmaddr);

}



static inline void flush_icache_page(struct vm_area_struct *vma,

	struct page *page)

static inline void flush_icache_pages(struct vm_area_struct *vma,

		struct page *page, unsigned int nr)

{

}

#define flush_icache_page(vma, page) flush_icache_pages(vma, page, 1)



extern void (*flush_icache_range)(unsigned long start, unsigned long end);

extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);

arch/mips/include/asm/pgtable-32.h

+5 −5
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static inline void pmd_clear(pmd_t *pmdp) 
#if defined(CONFIG_XPA)



#define MAX_POSSIBLE_PHYSMEM_BITS 40

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> PFN_PTE_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

static inline pte_t

pfn_pte(unsigned long pfn, pgprot_t prot)

{
@@ -161,7 +161,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 


	pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |

				(pgprot_val(prot) & ~_PFNX_MASK);

	pte.pte_high = (pfn << _PFN_SHIFT) |

	pte.pte_high = (pfn << PFN_PTE_SHIFT) |

				(pgprot_val(prot) & ~_PFN_MASK);

	return pte;

}
@@ -184,9 +184,9 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 
#else



#define MAX_POSSIBLE_PHYSMEM_BITS 32

#define pte_pfn(x)		((unsigned long)((x).pte >> _PFN_SHIFT))

#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))

#define pfn_pmd(pfn, prot)	__pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))

#define pte_pfn(x)		((unsigned long)((x).pte >> PFN_PTE_SHIFT))

#define pfn_pte(pfn, prot)	__pte(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))

#define pfn_pmd(pfn, prot)	__pmd(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))

#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */



#define pte_page(x)		pfn_to_page(pte_pfn(x))

arch/mips/include/asm/pgtable-64.h

+3 −3
Original line number Diff line number Diff line
@@ -298,9 +298,9 @@ static inline void pud_clear(pud_t *pudp) 


#define pte_page(x)		pfn_to_page(pte_pfn(x))



#define pte_pfn(x)		((unsigned long)((x).pte >> _PFN_SHIFT))

#define pfn_pte(pfn, prot)	__pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))

#define pfn_pmd(pfn, prot)	__pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot))

#define pte_pfn(x)		((unsigned long)((x).pte >> PFN_PTE_SHIFT))

#define pfn_pte(pfn, prot)	__pte(((pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))

#define pfn_pmd(pfn, prot)	__pmd(((pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))



#ifndef __PAGETABLE_PMD_FOLDED

static inline pmd_t *pud_pgtable(pud_t pud)

arch/mips/include/asm/pgtable-bits.h

+3 −3
Original line number Diff line number Diff line
@@ -182,10 +182,10 @@ enum pgtable_bits { 
#if defined(CONFIG_CPU_R3K_TLB)

# define _CACHE_UNCACHED	(1 << _CACHE_UNCACHED_SHIFT)

# define _CACHE_MASK		_CACHE_UNCACHED

# define _PFN_SHIFT		PAGE_SHIFT

# define PFN_PTE_SHIFT		PAGE_SHIFT

#else

# define _CACHE_MASK		(7 << _CACHE_SHIFT)

# define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)

# define PFN_PTE_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)

#endif



#ifndef _PAGE_NO_EXEC
@@ -195,7 +195,7 @@ enum pgtable_bits { 
#define _PAGE_SILENT_READ	_PAGE_VALID

#define _PAGE_SILENT_WRITE	_PAGE_DIRTY



#define _PFN_MASK		(~((1 << (_PFN_SHIFT)) - 1))

#define _PFN_MASK		(~((1 << (PFN_PTE_SHIFT)) - 1))



/*

 * The final layouts of the PTE bits are: