Commit 15d45cce authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: Replace use of phys_t with phys_addr_t. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 34adb28d

arch/mips/alchemy/common/setup.c

+2 −2
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ void __init plat_mem_setup(void) 


#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

/* This routine should be valid for all Au1x based boards */

phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)

phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	unsigned long start = ALCHEMY_PCI_MEMWIN_START;

	unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@@ -83,7 +83,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 


	/* Check for PCI memory window */

	if (phys_addr >= start && (phys_addr + size - 1) <= end)

		return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);

		return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);



	/* default nop */

	return phys_addr;

arch/mips/cavium-octeon/dma-octeon.c

+2 −2
Original line number Diff line number Diff line
@@ -262,8 +262,8 @@ char *octeon_swiotlb; 
void __init plat_swiotlb_setup(void)

{

	int i;

	phys_t max_addr;

	phys_t addr_size;

	phys_addr_t max_addr;

	phys_addr_t addr_size;

	size_t swiotlbsize;

	unsigned long swiotlb_nslabs;

arch/mips/include/asm/bootinfo.h

+4 −4
Original line number Diff line number Diff line
@@ -98,16 +98,16 @@ extern unsigned long mips_machtype; 
struct boot_mem_map {

	int nr_map;

	struct boot_mem_map_entry {

		phys_t addr;	/* start of memory segment */

		phys_t size;	/* size of memory segment */

		phys_addr_t addr;	/* start of memory segment */

		phys_addr_t size;	/* size of memory segment */

		long type;		/* type of memory segment */

	} map[BOOT_MEM_MAP_MAX];

};



extern struct boot_mem_map boot_mem_map;



extern void add_memory_region(phys_t start, phys_t size, long type);

extern void detect_memory_region(phys_t start, phys_t sz_min,  phys_t sz_max);

extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);

extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min,  phys_addr_t sz_max);



extern void prom_init(void);

extern void prom_free_prom_memory(void);

arch/mips/include/asm/io.h

+4 −4
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ static inline void * isa_bus_to_virt(unsigned long address) 
 */

#define page_to_phys(page)	((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)



extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);

extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);

extern void __iounmap(const volatile void __iomem *addr);



#ifndef CONFIG_PCI
@@ -175,7 +175,7 @@ struct pci_dev; 
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}

#endif



static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,

static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,

	unsigned long flags)

{

	void __iomem *addr = plat_ioremap(offset, size, flags);
@@ -183,7 +183,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 
	if (addr)

		return addr;



#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))

#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))



	if (cpu_has_64bit_addresses) {

		u64 base = UNCAC_BASE;
@@ -197,7 +197,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 
		return (void __iomem *) (unsigned long) (base + offset);

	} else if (__builtin_constant_p(offset) &&

		   __builtin_constant_p(size) && __builtin_constant_p(flags)) {

		phys_t phys_addr, last_addr;

		phys_addr_t phys_addr, last_addr;



		phys_addr = fixup_bigphys_addr(offset, size);

arch/mips/include/asm/mach-au1x00/ioremap.h

+4 −4
Original line number Diff line number Diff line
@@ -12,9 +12,9 @@ 
#include <linux/types.h>



#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)

extern phys_t __fixup_bigphys_addr(phys_t, phys_t);

extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);

#else

static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)

static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return phys_addr;

}
@@ -23,12 +23,12 @@ static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 
/*

 * Allow physical addresses to be fixed up to help 36-bit peripherals.

 */

static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)

static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)

{

	return __fixup_bigphys_addr(phys_addr, size);

}



static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,

static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,

	unsigned long flags)

{

	return NULL;