Commit 15a57448 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2023-02-01' of... 

Merge tag 'drm-intel-gt-next-2023-02-01' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

Fixes/improvements/new stuff:

- Fix bcs default context on Meteorlake (Lucas De Marchi)
- GAM registers don't need to be re-applied on engine resets (Matt Roper)
- Correct implementation of Wa_18018781329 (Matt Roper)
- Avoid potential vm use-after-free (Rob Clark)
- GuC error capture fixes (John Harrison)
- Fix potential bit_17 double-free (Rob Clark)
- Don't complain about missing regs on MTL (John Harrison)

Future platform enablement:

- Convert PSS_MODE2 to multicast register (Gustavo Sousa)
- Move/adjust register definitions related to Wa_22011450934 (Matt Roper)
- Move LSC_CHICKEN_BIT* workarounds to correct function (Gustavo Sousa)
- Document where to implement register workarounds (Gustavo Sousa)
- Use uabi engines for the default engine map (Tvrtko Ursulin)
- Flush all tiles on test exit (Tvrtko Ursulin)
- Annotate a couple more workaround registers as MCR (Matt Roper)

Driver refactors:

- Add and use GuC oriented print macros (Michal Wajdeczko)

Miscellaneous:

- Fix intel_selftest_modify_policy argument types (Arnd Bergmann)

Backmerges:

Merge drm/drm-next into drm-intel-gt-next (for conflict resolution) (Tvrtko Ursulin)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y9pOsq7VKnq7rgnW@tursulin-desk
parents 535cd710 003e11ed

drivers/gpu/drm/i915/gem/i915_gem_context.c

+15 −8
Original line number Diff line number Diff line
@@ -1096,16 +1096,15 @@ static struct i915_gem_engines *alloc_engines(unsigned int count) 
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,

						struct intel_sseu rcs_sseu)

{

	const struct intel_gt *gt = to_gt(ctx->i915);

	const unsigned int max = I915_NUM_ENGINES;

	struct intel_engine_cs *engine;

	struct i915_gem_engines *e, *err;

	enum intel_engine_id id;



	e = alloc_engines(I915_NUM_ENGINES);

	e = alloc_engines(max);

	if (!e)

		return ERR_PTR(-ENOMEM);



	for_each_engine(engine, gt, id) {

	for_each_uabi_engine(engine, ctx->i915) {

		struct intel_context *ce;

		struct intel_sseu sseu = {};

		int ret;
@@ -1113,7 +1112,7 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx, 
		if (engine->legacy_idx == INVALID_ENGINE)

			continue;



		GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);

		GEM_BUG_ON(engine->legacy_idx >= max);

		GEM_BUG_ON(e->engines[engine->legacy_idx]);



		ce = intel_context_create(engine);
@@ -1861,11 +1860,19 @@ static int get_ppgtt(struct drm_i915_file_private *file_priv, 
	vm = ctx->vm;

	GEM_BUG_ON(!vm);



	/*

	 * Get a reference for the allocated handle.  Once the handle is

	 * visible in the vm_xa table, userspace could try to close it

	 * from under our feet, so we need to hold the extra reference

	 * first.

	 */

	i915_vm_get(vm);



	err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);

	if (err)

	if (err) {

		i915_vm_put(vm);

		return err;



	i915_vm_get(vm);

	}



	GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */

	args->value = id;

drivers/gpu/drm/i915/gem/i915_gem_tiling.c

+5 −4
Original line number Diff line number Diff line
@@ -305,10 +305,6 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, 
	spin_unlock(&obj->vma.lock);



	obj->tiling_and_stride = tiling | stride;

	i915_gem_object_unlock(obj);



	/* Force the fence to be reacquired for GTT access */

	i915_gem_object_release_mmap_gtt(obj);



	/* Try to preallocate memory required to save swizzling on put-pages */

	if (i915_gem_object_needs_bit17_swizzle(obj)) {
@@ -321,6 +317,11 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, 
		obj->bit_17 = NULL;

	}



	i915_gem_object_unlock(obj);



	/* Force the fence to be reacquired for GTT access */

	i915_gem_object_release_mmap_gtt(obj);



	return 0;

}

drivers/gpu/drm/i915/gt/intel_context.c

+3 −1
Original line number Diff line number Diff line
@@ -528,7 +528,7 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) 
	return rq;

}



struct i915_request *intel_context_find_active_request(struct intel_context *ce)

struct i915_request *intel_context_get_active_request(struct intel_context *ce)

{

	struct intel_context *parent = intel_context_to_parent(ce);

	struct i915_request *rq, *active = NULL;
@@ -552,6 +552,8 @@ struct i915_request *intel_context_find_active_request(struct intel_context *ce) 


		active = rq;

	}

	if (active)

		active = i915_request_get_rcu(active);

	spin_unlock_irqrestore(&parent->guc_state.lock, flags);



	return active;

drivers/gpu/drm/i915/gt/intel_context.h

+1 −2
Original line number Diff line number Diff line
@@ -268,8 +268,7 @@ int intel_context_prepare_remote_request(struct intel_context *ce, 


struct i915_request *intel_context_create_request(struct intel_context *ce);



struct i915_request *

intel_context_find_active_request(struct intel_context *ce);

struct i915_request *intel_context_get_active_request(struct intel_context *ce);



static inline bool intel_context_is_barrier(const struct intel_context *ce)

{

drivers/gpu/drm/i915/gt/intel_engine.h

+2 −2
Original line number Diff line number Diff line
@@ -250,8 +250,8 @@ void intel_engine_dump_active_requests(struct list_head *requests, 
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,

				   ktime_t *now);



struct i915_request *

intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine);

void intel_engine_get_hung_entity(struct intel_engine_cs *engine,

				  struct intel_context **ce, struct i915_request **rq);



u32 intel_engine_context_size(struct intel_gt *gt, u8 class);

struct intel_context *