Commit 158c774d authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Thomas Bogendoerfer
Browse files

MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. 



1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
  nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
  nodes for CU1830-Neo.

Tested-by: default avatar周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780
Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 7701f264

arch/mips/boot/dts/ingenic/ci20.dts

+42 −3
Original line number Diff line number Diff line
@@ -69,9 +69,11 @@ 


	eth0_power: fixedregulator@0 {

		compatible = "regulator-fixed";



		regulator-name = "eth0_power";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpb 25 GPIO_ACTIVE_LOW>;

		enable-active-high;

	};
@@ -83,16 +85,39 @@ 


	wlan0_power: fixedregulator@1 {

		compatible = "regulator-fixed";



		regulator-name = "wlan0_power";



		gpio = <&gpb 19 GPIO_ACTIVE_LOW>;

		enable-active-high;

	};



	otg_power: fixedregulator@2 {

		compatible = "regulator-fixed";



		regulator-name = "otg_power";

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;



		gpio = <&gpf 14 GPIO_ACTIVE_LOW>;

		enable-active-high;

	};

};



&ext {

	clock-frequency = <48000000>;

};



&cgu {

	/*

	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher

	 * precision.

	 */

	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;

	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;

	assigned-clock-rates = <48000000>;

};



&mmc0 {

	status = "okay";
@@ -396,6 +421,16 @@ 
	status = "okay";

};



&otg_phy {

	status = "okay";



	vcc-supply = <&otg_power>;

};



&otg {

	status = "okay";

};



&pinctrl {

	pins_uart0: uart0 {

		function = "uart0";
@@ -489,7 +524,11 @@ 
};



&tcu {

	/* 3 MHz for the system timer and clocksource */

	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;

	assigned-clock-rates = <3000000>, <3000000>;

	/*

	 * 750 kHz for the system timer and 3 MHz for the clocksource,

	 * use channel #0 for the system timer, #1 for the clocksource.

	 */

	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,

					  <&tcu TCU_CLK_OST>;

	assigned-clock-rates = <750000>, <3000000>, <3000000>;

};

arch/mips/boot/dts/ingenic/cu1000-neo.dts

+56 −6
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 


#include "x1000.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/ingenic,tcu.h>

#include <dt-bindings/clock/ingenic,sysost.h>

#include <dt-bindings/interrupt-controller/irq.h>



/ {
@@ -31,6 +31,42 @@ 
		};

	};



	ssi: spi-gpio {

		compatible = "spi-gpio";

		#address-cells = <1>;

		#size-cells = <0>;

		num-chipselects = <1>;



		mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;

		miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;

		sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;

		cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;



		status = "okay";



		spi-max-frequency = <50000000>;



		sc16is752: expander@0 {

			compatible = "nxp,sc16is752";

			reg = <0>; /* CE0 */

			spi-max-frequency = <4000000>;



			clocks = <&exclk_sc16is752>;



			interrupt-parent = <&gpc>;

			interrupts = <6 IRQ_TYPE_EDGE_FALLING>;



			gpio-controller;

			#gpio-cells = <2>;



			exclk_sc16is752: sc16is752 {

				compatible = "fixed-clock";

				#clock-cells = <0>;

				clock-frequency = <48000000>;

			};

		};

	};



	wlan_pwrseq: msc1-pwrseq {

		compatible = "mmc-pwrseq-simple";
@@ -43,13 +79,19 @@ 
	clock-frequency = <24000000>;

};



&tcu {

&cgu {

	/*

	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher

	 * precision.

	 */

	assigned-clocks = <&cgu X1000_CLK_RTC>;

	assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;

};



&ost {

	/* 1500 kHz for the system timer and clocksource */

	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;

	assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;

	assigned-clock-rates = <1500000>, <1500000>;



	/* Use channel #0 for the system timer channel #2 for the clocksource */

	ingenic,pwm-channels-mask = <0xfa>;

};



&uart2 {
@@ -135,6 +177,14 @@ 
	};

};



&otg_phy {

	status = "okay";

};



&otg {

	status = "okay";

};



&pinctrl {

	pins_uart2: uart2 {

		function = "uart2";

arch/mips/boot/dts/ingenic/cu1830-neo.dts

+60 −6
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 


#include "x1830.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/ingenic,tcu.h>

#include <dt-bindings/clock/ingenic,sysost.h>

#include <dt-bindings/interrupt-controller/irq.h>



/ {
@@ -31,6 +31,42 @@ 
		};

	};



	ssi0: spi-gpio {

		compatible = "spi-gpio";

		#address-cells = <1>;

		#size-cells = <0>;

		num-chipselects = <1>;



		mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;

		miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;

		sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;

		cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;



		status = "okay";



		spi-max-frequency = <50000000>;



		sc16is752: expander@0 {

			compatible = "nxp,sc16is752";

			reg = <0>; /* CE0 */

			spi-max-frequency = <4000000>;



			clocks = <&exclk_sc16is752>;



			interrupt-parent = <&gpb>;

			interrupts = <18 IRQ_TYPE_EDGE_FALLING>;



			gpio-controller;

			#gpio-cells = <2>;



			exclk_sc16is752: sc16is752 {

				compatible = "fixed-clock";

				#clock-cells = <0>;

				clock-frequency = <48000000>;

			};

		};

	};



	wlan_pwrseq: msc1-pwrseq {

		compatible = "mmc-pwrseq-simple";
@@ -43,13 +79,19 @@ 
	clock-frequency = <24000000>;

};



&tcu {

&cgu {

	/*

	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher

	 * precision.

	 */

	assigned-clocks = <&cgu X1830_CLK_RTC>;

	assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;

};



&ost {

	/* 1500 kHz for the system timer and clocksource */

	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;

	assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;

	assigned-clock-rates = <1500000>, <1500000>;



	/* Use channel #0 for the system timer channel #2 for the clocksource */

	ingenic,pwm-channels-mask = <0xfa>;

};



&uart1 {
@@ -73,6 +115,10 @@ 
	};

};



&dtrng {

	status = "okay";

};



&msc0 {

	status = "okay";
@@ -135,6 +181,14 @@ 
	};

};



&otg_phy {

	status = "okay";

};



&otg {

	status = "okay";

};



&pinctrl {

	pins_uart1: uart1 {

		function = "uart1";

arch/mips/boot/dts/ingenic/jz4780.dtsi

+43 −2
Original line number Diff line number Diff line
@@ -61,13 +61,34 @@ 
	};



	cgu: jz4780-cgu@10000000 {

		compatible = "ingenic,jz4780-cgu";

		compatible = "ingenic,jz4780-cgu", "simple-mfd";

		reg = <0x10000000 0x100>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x10000000 0x100>;



		#clock-cells = <1>;



		clocks = <&ext>, <&rtc>;

		clock-names = "ext", "rtc";



		#clock-cells = <1>;

		otg_phy: usb-phy@3c {

			compatible = "ingenic,jz4780-phy";

			reg = <0x3c 0x10>;



			clocks = <&cgu JZ4780_CLK_OTG1>;



			#phy-cells = <0>;



			status = "disabled";

		};



		rng: rng@d8 {

			compatible = "ingenic,jz4780-rng";

			reg = <0xd8 0x8>;



			status = "disabled";

		};

	};



	tcu: timer@10002000 {
@@ -494,4 +515,24 @@ 


		status = "disabled";

	};



	otg: usb@13500000 {

		compatible = "ingenic,jz4780-otg", "snps,dwc2";

		reg = <0x13500000 0x40000>;



		interrupt-parent = <&intc>;

		interrupts = <21>;



		clocks = <&cgu JZ4780_CLK_UHC>;

		clock-names = "otg";



		phys = <&otg_phy>;

		phy-names = "usb2-phy";



		g-rx-fifo-size = <768>;

		g-np-tx-fifo-size = <256>;

		g-tx-fifo-size = <256 256 256 256 256 256 256 512>;



		status = "disabled";

	};

};

arch/mips/boot/dts/ingenic/x1000.dtsi

+55 −1
Original line number Diff line number Diff line
@@ -52,13 +52,47 @@ 
	};



	cgu: x1000-cgu@10000000 {

		compatible = "ingenic,x1000-cgu";

		compatible = "ingenic,x1000-cgu", "simple-mfd";

		reg = <0x10000000 0x100>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x10000000 0x100>;



		#clock-cells = <1>;



		clocks = <&exclk>, <&rtclk>;

		clock-names = "ext", "rtc";



		otg_phy: usb-phy@3c {

			compatible = "ingenic,x1000-phy";

			reg = <0x3c 0x10>;



			clocks = <&cgu X1000_CLK_OTGPHY>;



			#phy-cells = <0>;



			status = "disabled";

		};



		rng: rng@d8 {

			compatible = "ingenic,x1000-rng";

			reg = <0xd8 0x8>;



			status = "disabled";

		};

	};



	ost: timer@12000000 {

		compatible = "ingenic,x1000-ost";

		reg = <0x12000000 0x3c>;



		#clock-cells = <1>;



		clocks = <&cgu X1000_CLK_OST>;

		clock-names = "ost";



		interrupt-parent = <&cpuintc>;

		interrupts = <3>;

	};



	tcu: timer@10002000 {
@@ -323,4 +357,24 @@ 
			status = "disabled";

		};

	};



	otg: usb@13500000 {

		compatible = "ingenic,x1000-otg", "snps,dwc2";

		reg = <0x13500000 0x40000>;



		interrupt-parent = <&intc>;

		interrupts = <21>;



		clocks = <&cgu X1000_CLK_OTG>;

		clock-names = "otg";



		phys = <&otg_phy>;

		phy-names = "usb2-phy";



		g-rx-fifo-size = <768>;

		g-np-tx-fifo-size = <256>;

		g-tx-fifo-size = <256 256 256 256 256 256 256 512>;



		status = "disabled";

	};

};