media: dt-bindings: media: document allegro-dvt bindings

Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx

ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265

decoder ip core.

Each actual codec engines is controlled by a microcontroller (MCU). Host

software uses a provided mailbox interface to communicate with the MCU. The

MCU share an interrupt.

Required properties:

  - compatible: value should be one of the following

    "allegro,al5e-1.1", "allegro,al5e": encoder IP core

    "allegro,al5d-1.1", "allegro,al5d": decoder IP core

  - reg: base and length of the memory mapped register region and base and

    length of the memory mapped sram

  - reg-names: must include "regs" and "sram"

  - interrupts: shared interrupt from the MCUs to the processing system

  - clocks: must contain an entry for each entry in clock-names

  - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",

    "m_axi_mcu_aclk", "s_axi_lite_aclk"

Example:

	al5e: video-codec@a0009000 {

		compatible = "allegro,al5e-1.1", "allegro,al5e";

		reg = <0 0xa0009000 0 0x1000>,

		      <0 0xa0000000 0 0x8000>;

		reg-names = "regs", "sram";

		interrupts = <0 96 4>;

		clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,

			 <&clkc 71>, <&clkc 71>, <&clkc 71>;

		clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",

			      "m_axi_mcu_aclk", "s_axi_lite_aclk"

	};

	al5d: video-codec@a0029000 {

		compatible = "allegro,al5d-1.1", "allegro,al5d";

		reg = <0 0xa0029000 0 0x1000>,

		      <0 0xa0020000 0 0x8000>;

		reg-names = "regs", "sram";

		interrupts = <0 96 4>;

		clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,

			 <&clkc 71>, <&clkc 71>, <&clkc 71>;

		clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",

			      "m_axi_mcu_aclk", "s_axi_lite_aclk"

	};