Commit 155c6b16 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.3-2023-01-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.3-2023-01-27:

amdgpu:
- GC11 fixes
- SMU13 fixes
- Freesync fixes
- DP MST fixes
- DP MST code rework and cleanup
- AV1 fixes for VCN4
- DCN 3.2.x fixes
- PSR fixes
- DML optimizations
- DC link code rework

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230127225917.2419162-1-alexander.deucher@amd.com
parents dae437d5 cdf657fc

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+12 −0
Original line number Diff line number Diff line
@@ -3038,6 +3038,18 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) 
		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))

			continue;



		/* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.

		 * These are in TMR, hence are expected to be reused by PSP-TOS to reload

		 * from this location and RLC Autoload automatically also gets loaded

		 * from here based on PMFW -> PSP message during re-init sequence.

		 * Therefore, the psp suspend & resume should be skipped to avoid destroy

		 * the TMR and reload FWs again for IMU enabled APU ASICs.

		 */

		if (amdgpu_in_reset(adev) &&

		    (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)

			continue;



		/* XXX handle errors */

		r = adev->ip_blocks[i].version->funcs->suspend(adev);

		/* XXX handle errors */

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+2 −2
Original line number Diff line number Diff line
@@ -549,8 +549,8 @@ struct amdgpu_mst_connector { 


	struct drm_dp_mst_topology_mgr mst_mgr;

	struct amdgpu_dm_dp_aux dm_dp_aux;

	struct drm_dp_mst_port *port;

	struct amdgpu_connector *mst_port;

	struct drm_dp_mst_port *mst_output_port;

	struct amdgpu_connector *mst_root;

	bool is_mst_connector;

	struct amdgpu_encoder *mst_encoder;

};

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin"); 
MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");



static int imu_v11_0_init_microcode(struct amdgpu_device *adev)

{

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+2 −1
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 
MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");

MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");



static int mes_v11_0_hw_fini(void *handle);

static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
@@ -196,7 +198,6 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 
	mes_add_queue_pkt.trap_handler_addr = input->tba_addr;

	mes_add_queue_pkt.tma_addr = input->tma_addr;

	mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;

	mes_add_queue_pkt.trap_en = 1;



	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */

	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;

drivers/gpu/drm/amd/amdgpu/soc21.c

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_ 
{

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =