Commit 152520cb authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'fpga-for-5.20-rc1' of... 

Merge tag 'fpga-for-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga

 into char-misc-next

Xu writes:

Here is the first set of FPGA changes for 5.20-rc1

FPGA static firmware loader

- Russ's change to add support for Intel MAX10 BMC Secure
  Update driver which instantiates the new Firmware Upload
  functionality (merged on last cycle) of the Firmware
  Loader.

DFL

- keliu's change to use ida_alloc()/ida_free() instead of
  deprecated ida_simple_get()/ida_simple_remove()

ALTERA

- Marco's change to fix a "comparison with less than zero"
  warning

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: default avatarXu Yilun <yilun.xu@intel.com>

* tag 'fpga-for-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
  fpga: altera-pr-ip: fix unsigned comparison with less than zero
  fpga: Directly use ida_alloc()/free()
  fpga: m10bmc-sec: add max10 secure update functions
  fpga: m10bmc-sec: expose max10 canceled keys in sysfs
  fpga: m10bmc-sec: expose max10 flash update count
  fpga: m10bmc-sec: create max10 bmc secure update
  mfd: intel-m10-bmc: Rename n3000bmc-secure driver
parents a111daf0 2df84a75

Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update

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What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns the root entry hash for the static

		region if one is programmed, else it returns the

		string: "hash not programmed".  This file is only

		visible if the underlying device supports it.

		Format: string.



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns the root entry hash for the partial

		reconfiguration region if one is programmed, else it

		returns the string: "hash not programmed".  This file

		is only visible if the underlying device supports it.

		Format: string.



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns the root entry hash for the BMC image

		if one is programmed, else it returns the string:

		"hash not programmed".  This file is only visible if the

		underlying device supports it.

		Format: string.



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns a list of indices for canceled code

		signing keys for the static region. The standard bitmap

		list format is used (e.g. "1,2-6,9").



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns a list of indices for canceled code

		signing keys for the partial reconfiguration region. The

		standard bitmap list format is used (e.g. "1,2-6,9").



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns a list of indices for canceled code

		signing keys for the BMC.  The standard bitmap list format

		is used (e.g. "1,2-6,9").



What:		/sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count

Date:		Sep 2022

KernelVersion:	5.20

Contact:	Russ Weight <russell.h.weight@intel.com>

Description:	Read only. Returns number of times the secure update

		staging area has been flashed.

		Format: "%u".

MAINTAINERS

+7 −0
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@@ -7815,6 +7815,13 @@ F: Documentation/fpga/ 
F:	drivers/fpga/

F:	include/linux/fpga/









INTEL MAX10 BMC SECURE UPDATES









M:	Russ Weight <russell.h.weight@intel.com>









L:	linux-fpga@vger.kernel.org









S:	Maintained









F:	Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update









F:	drivers/fpga/intel-m10-bmc-sec-update.c

















FPU EMULATOR









M:	Bill Metzenthen <billm@melbpc.org.au>









S:	Maintained
































drivers/fpga/Kconfig



+12
−0






























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@@ -243,4 +243,16 @@ config FPGA_MGR_VERSAL_FPGA







	  configure the programmable logic(PL).



















	  To compile this as a module, choose M here.



















config FPGA_M10_BMC_SEC_UPDATE









	tristate "Intel MAX10 BMC Secure Update driver"









	depends on MFD_INTEL_M10_BMC && FW_UPLOAD









	help









	  Secure update support for the Intel MAX10 board management









	  controller.



















	  This is a subdriver of the Intel MAX10 board management controller









	  (BMC) and provides support for secure updates for the BMC image,









	  the FPGA image, the Root Entry Hashes, etc.



















endif # FPGA
























drivers/fpga/Makefile



+3
−0






























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@@ -22,6 +22,9 @@ obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o







obj-$(CONFIG_ALTERA_PR_IP_CORE)		+= altera-pr-ip-core.o









obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)	+= altera-pr-ip-core-plat.o



















# FPGA Secure Update Drivers









obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE)	+= intel-m10-bmc-sec-update.o



















# FPGA Bridge Drivers









obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o









obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
































drivers/fpga/altera-pr-ip-core.c



+1
−1






























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@@ -108,7 +108,7 @@ static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,







	u32 *buffer_32 = (u32 *)buf;









	size_t i = 0;



















	if (count <= 0)









	if (!count)









		return -EINVAL;



















	/* Write out the complete 32-bit chunks */