Merge tag 'clk-meson-v5.16-1' of https://github.com/BayLibre/clk-meson into clk-amlogic (151a994f) · Commits · EulixOS / Software / Kernel

drivers/clk/meson/meson8b.c

+119 −44

Original line number	Diff line number	Diff line
		@@ -118,6 +118,56 @@ static struct clk_regmap meson8b_fixed_pll = {
		},
		};

		static struct clk_fixed_factor hdmi_pll_dco_in = {
		.mult = 2,
		.div = 1,
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_pll_dco_in",
		.ops = &clk_fixed_factor_ops,
		.parent_data = &(const struct clk_parent_data) {
		.fw_name = "xtal",
		.index = -1,
		},
		.num_parents = 1,
		},
		};

		/*
		* Taken from the vendor driver for the 2970/2975MHz (both only differ in the
		* FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8,
		* Meson8b and Meson8m2. This doubles the input (or output - it's not clear
		* which one but the result is the same) clock. The vendor driver additionally
		* has the following comment about: "optimise HPLL VCO 2.97GHz performance".
		*/
		static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = {
		{ .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 },
		{ .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 },
		{ .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 },
		{ .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 },
		{ .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 },
		};

		static const struct pll_params_table hdmi_pll_params_table[] = {
		PLL_PARAMS(40, 1),
		PLL_PARAMS(42, 1),
		PLL_PARAMS(44, 1),
		PLL_PARAMS(45, 1),
		PLL_PARAMS(49, 1),
		PLL_PARAMS(52, 1),
		PLL_PARAMS(54, 1),
		PLL_PARAMS(56, 1),
		PLL_PARAMS(59, 1),
		PLL_PARAMS(60, 1),
		PLL_PARAMS(61, 1),
		PLL_PARAMS(62, 1),
		PLL_PARAMS(64, 1),
		PLL_PARAMS(66, 1),
		PLL_PARAMS(68, 1),
		PLL_PARAMS(71, 1),
		PLL_PARAMS(82, 1),
		{ /* sentinel */ }
		};

		static struct clk_regmap meson8b_hdmi_pll_dco = {
		.data = &(struct meson_clk_pll_data){
		.en = {
		@@ -150,15 +200,16 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
		.shift = 29,
		.width = 1,
		},
		.table = hdmi_pll_params_table,
		.init_regs = meson8b_hdmi_pll_init_regs,
		.init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
		},
		.hw.init = &(struct clk_init_data){
		/* sometimes also called "HPLL" or "HPLL PLL" */
		.name = "hdmi_pll_dco",
		.ops = &meson_clk_pll_ro_ops,
		.parent_data = &(const struct clk_parent_data) {
		.fw_name = "xtal",
		.name = "xtal",
		.index = -1,
		.ops = &meson_clk_pll_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&hdmi_pll_dco_in.hw
		},
		.num_parents = 1,
		},
		@@ -173,7 +224,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_pll_lvds_out",
		.ops = &clk_regmap_divider_ro_ops,
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_hdmi_pll_dco.hw
		},
		@@ -191,7 +242,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_pll_hdmi_out",
		.ops = &clk_regmap_divider_ro_ops,
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_hdmi_pll_dco.hw
		},
		@@ -1045,6 +1096,23 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = {
		},
		};

		/* also called LVDS_CLK_EN */
		static struct clk_regmap meson8b_vid_pll_lvds_en = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_VID_DIVIDER_CNTL,
		.bit_idx = 11,
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_lvds_en",
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_hdmi_pll_lvds_out.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		static struct clk_regmap meson8b_vid_pll_in_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_VID_DIVIDER_CNTL,
		@@ -1053,7 +1121,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_in_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		/*
		* TODO: depending on the SoC there is also a second parent:
		* Meson8: unknown
		@@ -1061,7 +1129,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
		* Meson8m2: vid2_pll
		*/
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_hdmi_pll_lvds_out.hw
		&meson8b_vid_pll_lvds_en.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		@@ -1075,7 +1143,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_in_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vid_pll_in_sel.hw
		},
		@@ -1092,7 +1160,7 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_pre_div",
		.ops = &clk_regmap_divider_ro_ops,
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vid_pll_in_en.hw
		},
		@@ -1109,7 +1177,7 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_post_div",
		.ops = &clk_regmap_divider_ro_ops,
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vid_pll_pre_div.hw
		},
		@@ -1126,7 +1194,7 @@ static struct clk_regmap meson8b_vid_pll = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		/* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vid_pll_pre_div.hw,
		@@ -1145,7 +1213,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vid_pll_final_div",
		.ops = &clk_regmap_divider_ro_ops,
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vid_pll.hw
		},
		@@ -1172,10 +1240,10 @@ static struct clk_regmap meson8b_vclk_in_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_in_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
		},
		};

		@@ -1186,7 +1254,7 @@ static struct clk_regmap meson8b_vclk_in_en = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_in_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_in_sel.hw
		},
		@@ -1202,7 +1270,7 @@ static struct clk_regmap meson8b_vclk_en = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_in_en.hw
		},
		@@ -1218,7 +1286,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div1_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_en.hw
		},
		@@ -1248,7 +1316,7 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div2_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_div2_div.hw
		},
		@@ -1278,7 +1346,7 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div4_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_div4_div.hw
		},
		@@ -1308,7 +1376,7 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div6_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_div6_div.hw
		},
		@@ -1338,7 +1406,7 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk_div12_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk_div12_div.hw
		},
		@@ -1355,10 +1423,10 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_in_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
		},
		};

		@@ -1369,7 +1437,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_in_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_in_sel.hw
		},
		@@ -1385,7 +1453,7 @@ static struct clk_regmap meson8b_vclk2_clk_en = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_clk_in_en.hw
		},
		@@ -1401,7 +1469,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div1_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_clk_en.hw
		},
		@@ -1431,7 +1499,7 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div2_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_div2_div.hw
		},
		@@ -1461,7 +1529,7 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div4_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_div4_div.hw
		},
		@@ -1491,7 +1559,7 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div6_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_div6_div.hw
		},
		@@ -1521,7 +1589,7 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "vclk2_div12_en",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_vclk2_div12_div.hw
		},
		@@ -1546,7 +1614,7 @@ static struct clk_regmap meson8b_cts_enct_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_enct_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1560,7 +1628,7 @@ static struct clk_regmap meson8b_cts_enct = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_enct",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_cts_enct_sel.hw
		},
		@@ -1577,7 +1645,7 @@ static struct clk_regmap meson8b_cts_encp_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_encp_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1591,7 +1659,7 @@ static struct clk_regmap meson8b_cts_encp = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_encp",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_cts_encp_sel.hw
		},
		@@ -1608,7 +1676,7 @@ static struct clk_regmap meson8b_cts_enci_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_enci_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1622,7 +1690,7 @@ static struct clk_regmap meson8b_cts_enci = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_enci",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_cts_enci_sel.hw
		},
		@@ -1639,7 +1707,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_tx_pixel_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1653,7 +1721,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "hdmi_tx_pixel",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_hdmi_tx_pixel_sel.hw
		},
		@@ -1678,7 +1746,7 @@ static struct clk_regmap meson8b_cts_encl_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_encl_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1692,7 +1760,7 @@ static struct clk_regmap meson8b_cts_encl = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_encl",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_cts_encl_sel.hw
		},
		@@ -1709,7 +1777,7 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_vdac0_sel",
		.ops = &clk_regmap_mux_ro_ops,
		.ops = &clk_regmap_mux_ops,
		.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
		.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
		.flags = CLK_SET_RATE_PARENT,
		@@ -1723,7 +1791,7 @@ static struct clk_regmap meson8b_cts_vdac0 = {
		},
		.hw.init = &(struct clk_init_data){
		.name = "cts_vdac0",
		.ops = &clk_regmap_gate_ro_ops,
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&meson8b_cts_vdac0_sel.hw
		},
		@@ -2905,6 +2973,8 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
		[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
		[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
		[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
		[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
		[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
		[CLK_NR_CLKS] = NULL,
		},
		.num = CLK_NR_CLKS,
		@@ -3122,6 +3192,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
		[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
		[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
		[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
		[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
		[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
		[CLK_NR_CLKS] = NULL,
		},
		.num = CLK_NR_CLKS,
		@@ -3341,6 +3413,8 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
		[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
		[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
		[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
		[CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
		[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
		[CLK_NR_CLKS] = NULL,
		},
		.num = CLK_NR_CLKS,
		@@ -3539,6 +3613,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
		&meson8b_cts_mclk_i958_div,
		&meson8b_cts_mclk_i958,
		&meson8b_cts_i958,
		&meson8b_vid_pll_lvds_en,
		};

		static const struct meson8b_clk_reset_line {

drivers/clk/meson/meson8b.h

+14 −12

Original line number	Diff line number	Diff line
		@@ -51,6 +51,16 @@
		#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
		#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
		#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
		#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
		#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */
		#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
		#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
		#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */
		#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */
		#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */
		#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */
		#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */
		#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */

		/*
		* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
		@@ -108,13 +118,10 @@
		#define CLKID_AXI_SEL 127
		#define CLKID_L2_DRAM_SEL 129
		#define CLKID_HDMI_PLL_LVDS_OUT 131
		#define CLKID_HDMI_PLL_HDMI_OUT 132
		#define CLKID_VID_PLL_IN_SEL 133
		#define CLKID_VID_PLL_IN_EN 134
		#define CLKID_VID_PLL_PRE_DIV 135
		#define CLKID_VID_PLL_POST_DIV 136
		#define CLKID_VID_PLL_FINAL_DIV 137
		#define CLKID_VCLK_IN_SEL 138
		#define CLKID_VCLK_IN_EN 139
		#define CLKID_VCLK_DIV1 140
		#define CLKID_VCLK_DIV2_DIV 141
		@@ -125,7 +132,6 @@
		#define CLKID_VCLK_DIV6 146
		#define CLKID_VCLK_DIV12_DIV 147
		#define CLKID_VCLK_DIV12 148
		#define CLKID_VCLK2_IN_SEL 149
		#define CLKID_VCLK2_IN_EN 150
		#define CLKID_VCLK2_DIV1 151
		#define CLKID_VCLK2_DIV2_DIV 152
		@@ -137,17 +143,11 @@
		#define CLKID_VCLK2_DIV12_DIV 158
		#define CLKID_VCLK2_DIV12 159
		#define CLKID_CTS_ENCT_SEL 160
		#define CLKID_CTS_ENCT 161
		#define CLKID_CTS_ENCP_SEL 162
		#define CLKID_CTS_ENCP 163
		#define CLKID_CTS_ENCI_SEL 164
		#define CLKID_CTS_ENCI 165
		#define CLKID_HDMI_TX_PIXEL_SEL 166
		#define CLKID_HDMI_TX_PIXEL 167
		#define CLKID_CTS_ENCL_SEL 168
		#define CLKID_CTS_ENCL 169
		#define CLKID_CTS_VDAC0_SEL 170
		#define CLKID_CTS_VDAC0 171
		#define CLKID_HDMI_SYS_SEL 172
		#define CLKID_HDMI_SYS_DIV 173
		#define CLKID_MALI_0_SEL 175
		@@ -182,8 +182,10 @@
		#define CLKID_CTS_MCLK_I958_DIV 211
		#define CLKID_VCLK_EN 214
		#define CLKID_VCLK2_EN 215
		#define CLKID_VID_PLL_LVDS_EN 216
		#define CLKID_HDMI_PLL_DCO_IN 217

		#define CLK_NR_CLKS 216
		#define CLK_NR_CLKS 218

		/*
		* include the CLKID and RESETID that have

include/dt-bindings/clock/meson8b-clkc.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -105,6 +105,16 @@
		#define CLKID_PERIPH 126
		#define CLKID_AXI 128
		#define CLKID_L2_DRAM 130
		#define CLKID_HDMI_PLL_HDMI_OUT 132
		#define CLKID_VID_PLL_FINAL_DIV 137
		#define CLKID_VCLK_IN_SEL 138
		#define CLKID_VCLK2_IN_SEL 149
		#define CLKID_CTS_ENCT 161
		#define CLKID_CTS_ENCP 163
		#define CLKID_CTS_ENCI 165
		#define CLKID_HDMI_TX_PIXEL 167
		#define CLKID_CTS_ENCL 169
		#define CLKID_CTS_VDAC0 171
		#define CLKID_HDMI_SYS 174
		#define CLKID_VPU 190
		#define CLKID_VDEC_1 196